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Issue No. 01 - January/February (2009 vol. 29)
ISSN: 0272-1732
pp: 22-32
Onur Mutlu , Carnegie Mellon University
Thomas Moscibroda , Microsoft Research
<p>Uncontrolled interthread interference in main memory can destroy individual threads' memory-level parallelism, effectively serializing the memory requests of a thread whose latencies would otherwise have largely overlapped, thereby reducing single-thread performance. The parallelism-aware batch scheduler preserves each thread's memory-level parallelism, ensures fairness and starvation freedom, and supports system-level thread priorities.</p>
memory controllers, DRAM, memory-level parallelism, fairness, multicore, quality of service, chip multiprocessors.

O. Mutlu and T. Moscibroda, "Parallelism-Aware Batch Scheduling: Enabling High-Performance and Fair Shared Memory Controllers," in IEEE Micro, vol. 29, no. , pp. 22-32, 2009.
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