Issue No.06 - November/December (2008 vol.28)
Philip G. Emma , IBM T.J. Watson Research Center
William R. Reohr , IBM T.J. Watson Research Center
Mesut Meterelliyoz , IBM T.J. Watson Research Center
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/MM.2008.93
Caches use data very differently than main memory does, so DRAM caches can have dramatically different refresh requirements. Making canonical assumptions about retention times in DRAM can be drastic overkill within the cache context. Using standard refresh rates may be unnecessary and can be a significant waste of cache utilization and power. In this article, we view "retention time" in a new way by using statistical populations more appropriate for caches, and we suggest uses of a cache's inherent error-control mechanisms to reduce refresh rates by several orders of magnitude.
cache structures, DRAM, error-correction code, refresh rates
Philip G. Emma, William R. Reohr, Mesut Meterelliyoz, "Rethinking Refresh: Increasing Availability and Reducing Power in DRAM for Cache Applications", IEEE Micro, vol.28, no. 6, pp. 47-56, November/December 2008, doi:10.1109/MM.2008.93