The Community for Technology Leaders
Green Image
Issue No. 04 - July/August (2008 vol. 28)
ISSN: 0272-1732
pp: 51-70
Mei Wen , National University of Defense Technology, China
Nan Wu , National University of Defense Technology, China
Chunyuan Zhang , National University of Defense Technology, China
Qianming Yang , National University of Defense Technology, China
Jun Ren , National University of Defense Technology, China
Yi He , National University of Defense Technology, China
Wei Wu , National University of Defense Technology, China
Jun Chai , National University of Defense Technology, China
Maolin Guan , National University of Defense Technology, China
Changqing Xun , National University of Defense Technology, China
ABSTRACT
With the extension of application domains, hardware-managed memory structures such as caches are drawing attention for dealing with irregular stream applications. However, since a real application usually has both regular and irregular stream characteristics, conventional stream register files, caches, or combinations thereof have shortcomings. This article focuses on combining software- and hardware-managed memory structures and presents a new syncretic memory system based on the FT64 stream accelerator.
INDEX TERMS
stream architecture, cache, stream register file, irregular stream, scientific accelerator
CITATION

M. Wen et al., "On-Chip Memory System Optimization Design for the FT64 Scientific Stream Accelerator," in IEEE Micro, vol. 28, no. , pp. 51-70, 2008.
doi:10.1109/MM.2008.56
93 ms
(Ver 3.3 (11022016))