Issue No. 04 - July/August (2008 vol. 28)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/MM.2008.58
Dong Hyuk Woo , Georgia Institute of Technology
Hsien-Hsin S. Lee , Georgia Institute of Technology
Joshua B. Fryman , Intel
Allan D. Knies , Intel
Marsha Eng , Intel
To build a future many-core processor, industry must address the challenges of energy consumption and performance scalability. A 3D-integrated broad-purpose accelerator architecture called parallel-on-demand (POD) integrates a specialized SIMD-based die layer on top of a CISC superscalar processor to accelerate a variety of data-parallel applications. It also maintains binary compatibility and facilitates extensibility by virtualizing the acceleration capability.
multicore, multiprocessors, parallel architectures, processor architectures, computer systems organization, physically aware microarchitecture, microarchitecture implementation, processor architectures, power management
H. S. Lee, D. H. Woo, J. B. Fryman, M. Eng and A. D. Knies, "POD: A 3D-Integrated Broad-Purpose Acceleration Layer," in IEEE Micro, vol. 28, no. , pp. 28-40, 2008.