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Issue No. 04 - July/August (2008 vol. 28)
ISSN: 0272-1732
pp: 28-40
Hsien-Hsin S. Lee , Georgia Institute of Technology
Dong Hyuk Woo , Georgia Institute of Technology
Marsha Eng , Intel
ABSTRACT
To build a future many-core processor, industry must address the challenges of energy consumption and performance scalability. A 3D-integrated broad-purpose accelerator architecture called parallel-on-demand (POD) integrates a specialized SIMD-based die layer on top of a CISC superscalar processor to accelerate a variety of data-parallel applications. It also maintains binary compatibility and facilitates extensibility by virtualizing the acceleration capability.
INDEX TERMS
multicore, multiprocessors, parallel architectures, processor architectures, computer systems organization, physically aware microarchitecture, microarchitecture implementation, processor architectures, power management
CITATION
Hsien-Hsin S. Lee, Dong Hyuk Woo, Joshua B. Fryman, Marsha Eng, Allan D. Knies, "POD: A 3D-Integrated Broad-Purpose Acceleration Layer", IEEE Micro, vol. 28, no. , pp. 28-40, July/August 2008, doi:10.1109/MM.2008.58
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