The Community for Technology Leaders
Green Image
Issue No. 01 - January/February (2008 vol. 28)
ISSN: 0272-1732
pp: 60-68
Ramon Canal , Universitat Politècnica de Catalunya
Xiaoyao Liang , Harvard University
David Brooks , Harvard University
Gu-Yeon Wei , Harvard University
With continued technology scaling, process variations will be especially detrimental to six-transistor static memory structures (6T SRAMs). A memory architecture using three-transistor, one-diode DRAM (3T1D) cells in the L1 data cache tolerates wide process variations with little performance degradation, making it a promising choice for on-chip cache structures for next-generation microprocessors.
variability, process variation, caches, dynamic memory
Ramon Canal, Xiaoyao Liang, David Brooks, Gu-Yeon Wei, "Replacing 6T SRAMs with 3T1D DRAMs in the L1 Data Cache to Combat Process Variability", IEEE Micro, vol. 28, no. , pp. 60-68, January/February 2008, doi:10.1109/MM.2008.12
92 ms
(Ver 3.3 (11022016))