Issue No. 01 - January/February (2008 vol. 28)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/MM.2008.7
Naveen Neelakantam , University of Illinois at Urbana-Champaign
Ravi Rajwar , Intel
Suresh Srinivas , Intel
Uma Srinivasan , Intel
Craig Zilles , University of Illinois at Urbana-Champaign
Hardware support for atomic execution can both greatly simplify the implementation of existing speculative compiler optimizations and enable new ones. Given current technology trends, this hardware and software cooperation is a compelling approach; such optimizations can simultaneously improve single-thread performance and reduce power consumption in both sequential and multithreaded applications.
compiler-architecture interactions, architecture, atomicity, checkpoint, compiler, isolation, Java, optimization, speculation
C. Zilles, R. Rajwar, U. Srinivasan, S. Srinivas and N. Neelakantam, "Hardware Atomicity: An Effective Abstraction for Reliable Software Speculation," in IEEE Micro, vol. 28, no. , pp. 21-31, 2008.