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Issue No. 01 - January/February (vol. 28)
ISSN: 0272-1732

Virtual Hierarchies (Abstract)

M.R. Marty , Wisconsin Univ., Madison
M.D. Hill , Wisconsin Univ., Madison
pp. 99-109
Micro Economics

The Long Arc Behind Bill Gates' Wealth (Abstract)

Shane Greenstein , Kellogg Graduate School of Management
pp. 4-7

Guest Editors' Introduction: Top Picks from the Computer Architecture Conferences of 2007 (HTML)

David Brooks , Harvard
Craig Zilles , University of Illinois, Urbana-Champaign
Sarita Adve , University of Illinois, Urbana-Champaign
pp. 8-11

Revisiting the Sequential Programming Model for the Multicore Era (Abstract)

Thomas Jablin , Princeton University
Yun Zhang , Princeton University
Neil Vachharajani , Princeton University
David I. August , Princeton University
Matthew J. Bridges , Princeton University
pp. 12-20

Hardware Atomicity: An Effective Abstraction for Reliable Software Speculation (Abstract)

Craig Zilles , University of Illinois at Urbana-Champaign
Ravi Rajwar , Intel
Naveen Neelakantam , University of Illinois at Urbana-Champaign
pp. 21-31

Performance Pathologies in Hardware Transactional Memory (Abstract)

Kevin E. Moore , Sun Microsystems
Mark D. Hill , University of Wisconsin—Madison
Haris Volos , University of Wisconsin—Madison
David A. Wood , University of Wisconsin—Madison
Michael M. Swift , University of Wisconsin—Madison
Jayaram Bobba , University of Wisconsin—Madison
Luke Yen , University of Wisconsin—Madison
pp. 32-41

MetaTM/TxLinux: Transactional Memory for an Operating System (Abstract)

Owen S. Hofmann , University of Texas at Austin
Donald E. Porter , University of Texas at Austin
Emmett Witchel , University of Texas at Austin
Christopher J. Rossbach , University of Texas at Austin
Hany E. Ramadan , University of Texas at Austin
Aditya Bhandari , University of Texas at Austin
pp. 42-51

Argus: Low-Cost, Comprehensive Error Detection in Simple Cores (Abstract)

Daniel J. Sorin , Duke University
Michael E. Bauer , Duke University
Albert Meixner , Duke University
pp. 52-59

Replacing 6T SRAMs with 3T1D DRAMs in the L1 Data Cache to Combat Process Variability (Abstract)

Ramon Canal , Universitat Politècnica de Catalunya
Xiaoyao Liang , Harvard University
David Brooks , Harvard University
Gu-Yeon Wei , Harvard University
pp. 60-68

Architecting Efficient Interconnects for Large Caches with CACTI 6.0 (Abstract)

Naveen Muralimanohar , University of Utah
Rajeev Balasubramonian , University of Utah
Norman P. Jouppi , Hewlett-Packard Laboratories
pp. 69-79

Toward Ideal On-Chip Communication Using Express Virtual Channels (Abstract)

Partha Kundu , Microprocessor Technology Labs, Intel
Li-Shiuan Peh , Princeton University
Amit Kumar , Princeton University
Niraj K. Jha , Princeton University
pp. 80-90

Set-Dueling-Controlled Adaptive Insertion for High-Performance Caching (Abstract)

Moinuddin K. Qureshi , IBM Research
Aamer Jaleel , Intel
Joel Emer , Intel
Yale N. Patt , The University of Texas at Austin
pp. 91-98

Virtual Hierarchies (Abstract)

Michael R. Marty , University of Wisconsin—Madison
Mark D. Hill , University of Wisconsin—Madison
pp. 99-109
Micro Innovations

A Collaborative IP-Development Session (Abstract)

Philip Emma , IBM T.J. Watson Research Center
pp. 112, 110-111
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