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Issue No. 05 - September/October (2007 vol. 27)
ISSN: 0272-1732
pp: 75-85
Luca Benini , Università di Bologna
Federico Angiolini , Università di Bologna
Giovanni De Micheli , École Polytechnique Fédérale de Lausanne
Srinivasan Murali , École Polytechnique Fédérale de Lausanne
Antonio Pullini , Politecnico di Torino
David Atienza , Universidad Complutense de Madrid
ABSTRACT
Very deep submicron process technologies are ideal application fields for NoCs, which offer a promising solution to the scalability problem. This article sheds light on the benefits and challenges of NoC-based interconnect design in nanometer CMOS. The authors present experimental results from fully working 65-nm NoC designs and a detailed scalability analysis.
INDEX TERMS
network on chip, deep submicron design, on-chip interconnection networks, design aids, low-power design, power management, multicore architectures
CITATION
Luca Benini, Federico Angiolini, Giovanni De Micheli, Srinivasan Murali, Antonio Pullini, David Atienza, "Bringing NoCs to 65 nm", IEEE Micro, vol. 27, no. , pp. 75-85, September/October 2007, doi:10.1109/MM.2007.79
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