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Issue No. 05 - September/October (2007 vol. 27)
ISSN: 0272-1732
pp: 75-85
Antonio Pullini , Politecnico di Torino
Federico Angiolini , Università di Bologna
Srinivasan Murali , École Polytechnique Fédérale de Lausanne
David Atienza , Universidad Complutense de Madrid
Giovanni De Micheli , École Polytechnique Fédérale de Lausanne
Luca Benini , Università di Bologna
ABSTRACT
Very deep submicron process technologies are ideal application fields for NoCs, which offer a promising solution to the scalability problem. This article sheds light on the benefits and challenges of NoC-based interconnect design in nanometer CMOS. The authors present experimental results from fully working 65-nm NoC designs and a detailed scalability analysis.
INDEX TERMS
network on chip, deep submicron design, on-chip interconnection networks, design aids, low-power design, power management, multicore architectures
CITATION

L. Benini, F. Angiolini, G. De Micheli, S. Murali, A. Pullini and D. Atienza, "Bringing NoCs to 65 nm," in IEEE Micro, vol. 27, no. , pp. 75-85, 2007.
doi:10.1109/MM.2007.79
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