Issue No. 05 - September/October (2007 vol. 27)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/MM.2007.78
David Arditti Ilitzky , Intel
Jeffrey D. Hoffman , Intel
Anthony Chun , Intel
Brando Perez Esparza , Intel
The SCC is a flexible and energy- and area-efficient baseband processor for concurrent multiple wireless protocols. Its architecture consists of coarse-grained, heterogeneous, programmable accelerators connected via a packet-based, 3-ary 2-cube network on chip. The NoC supports goals of flexibility, scalability, and extensibility, and it meets stringent latency and throughput requirements.
wireless, wide-area networks, communication, networking, on-chip interconnection networks, multicore architectures, parallel architectures
B. Perez Esparza, D. Arditti Ilitzky, A. Chun and J. D. Hoffman, "Architecture of the Scalable Communications Core's Network on Chip," in IEEE Micro, vol. 27, no. , pp. 62-74, 2007.