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Issue No. 05 - September/October (2007 vol. 27)
ISSN: 0272-1732
pp: 62-74
Anthony Chun , Intel
ABSTRACT
The SCC is a flexible and energy- and area-efficient baseband processor for concurrent multiple wireless protocols. Its architecture consists of coarse-grained, heterogeneous, programmable accelerators connected via a packet-based, 3-ary 2-cube network on chip. The NoC supports goals of flexibility, scalability, and extensibility, and it meets stringent latency and throughput requirements.
INDEX TERMS
wireless, wide-area networks, communication, networking, on-chip interconnection networks, multicore architectures, parallel architectures
CITATION
Brando Perez Esparza, David Arditti Ilitzky, Anthony Chun, Jeffrey D. Hoffman, "Architecture of the Scalable Communications Core's Network on Chip", IEEE Micro, vol. 27, no. , pp. 62-74, September/October 2007, doi:10.1109/MM.2007.78
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