Issue No. 05 - September/October (2007 vol. 27)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/MM.2007.77
Yatin Hoskote , Intel
Sriram Vangal , Intel
Arvind Singh , Intel
Nitin Borkar , Intel
Shekhar Borkar , Intel
A multicore processor in 65-nm technology with 80 single-precision, floating-point cores delivers performance in excess of a teraflops while consuming less than 100 W. A 2D on-die mesh interconnection network operating at 5 GHz provides the high-performance communication fabric to connect the cores. The network delivers a bisection bandwidth of 2.56 Terabits per second and a per hop fall-through latency of 1 nanosecond.
CMOS digital integrated circuits, interconnection fabric, crossbar, mesh, router, network on chip
S. Vangal, A. Singh, S. Borkar, N. Borkar and Y. Hoskote, "A 5-GHz Mesh Interconnect for a Teraflops Processor," in IEEE Micro, vol. 27, no. , pp. 51-61, 2007.