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Issue No.05 - September/October (2007 vol.27)
pp: 51-61
Arvind Singh , Intel
Nitin Borkar , Intel
A multicore processor in 65-nm technology with 80 single-precision, floating-point cores delivers performance in excess of a teraflops while consuming less than 100 W. A 2D on-die mesh interconnection network operating at 5 GHz provides the high-performance communication fabric to connect the cores. The network delivers a bisection bandwidth of 2.56 Terabits per second and a per hop fall-through latency of 1 nanosecond.
CMOS digital integrated circuits, interconnection fabric, crossbar, mesh, router, network on chip
Yatin Hoskote, Sriram Vangal, Arvind Singh, Nitin Borkar, Shekhar Borkar, "A 5-GHz Mesh Interconnect for a Teraflops Processor", IEEE Micro, vol.27, no. 5, pp. 51-61, September/October 2007, doi:10.1109/MM.2007.77
1. L. Benini et al., "Networks on Chips: A New SoC Paradigm," Computer, vol. 35, no. 1, Jan. 2002, pp. 70-78.
2. W.J. Dally and B. Towles, "Route Packets, Not Wires: On-Chip Interconnection Networks," Proc. 38th Design Automation Conf. (DAC 01), ACM Press, 2001, pp. 681-689.
3. M.B. Taylor et al., "The Raw Microprocessor: A Computational Fabric for Software Circuits and General Purpose Programs," IEEE Micro, vol. 22, no. 2, Mar.-Apr. 2002, pp. 25-35.
4. K. Sankaralingam et al., "Exploiting ILP, TLP, and DLP with the Polymorphous TRIPS Architecture," Proc. 30th Ann. Int'l Symp. Computer Architecture (ISCA 03), IEEE CS Press, 2003, pp. 422-433.
5. Y. Zhiyi et al., "An Asynchronous Array of Simple Processors For DSP Applications," Proc. Int'l Solid-State Circuits Conf Dig. Tech. Papers (ISSCC 06), IEEE Press, 2006, pp. 428-429.
6. D.C. Pham et al., "Overview of the Architecture, Circuit Designs and Physical Implementation of a First Generation Cell Processor," IEEE J. Solid-State Circuits, vol. 41, no. 1, Jan. 2006, pp. 179-196.
7. P. Kongetira, K. Aingaran, and K. Olukotun, "Niagara: A 32-Way Multithreaded Sparc Processor," IEEE Micro, vol. 25, no. 2, Mar.-Apr. 2005, pp. 21-29.
8. S. Vangal et al., "An 80-Tile 1.28TFLOPS Network-on-Chip in 65 nm CMOS," Int'l Solid-State Circuits Conf Dig. Tech. Papers (ISSCC 07), IEEE Press, 2007, pp. 98-99.
9. S. Vangal et al., "A 6.2-GFlops Floating-Point Multiply-Accumulator with Conditional Normalization," IEEE J. Solid-State Circuits, vol. 41, no. 10, Oct. 2006, pp. 2314-2323.
10. W. Dally and C. Seitz, "Deadlock-Free Message Routing in Multiprocessor Interconnection Networks," IEEE Trans. Computers, vol. 36, no. 5, May 1987, pp. 547-553.
11. F. Klass, "Semi-Dynamic and Dynamic Flip-Flops with Embedded Logic," Proc. 1998 Symp. VLSI Circuits, Digest of Technical Papers, IEEE Press, 1998, pp. 108-109.
12. S. Vangal, N. Borkar, and A. Alvandpour, "A Six-Port 57GB/s Double-Pumped Non-blocking Router Core," Proc. Symp. VLSI Circuits, IEEE Press, 2005, pp. 268-269.
13. J.W. Cooley and J.W. Tukey, "An Algorithm for the Machine Calculation of Complex Fourier Series," Mathematics of Computation, vol. 19, 1965, pp. 297-301.
14. P. Bai et al., "A 65 nm Logic Technology Featuring 35 nm Gate Lengths, Enhanced Channel Strain, 8 Cu Interconnect Layers, Low-k ILD and 0.57 µm2 SRAM Cell," IEDM Tech. Dig.,, Dec. 2004, pp. 657-660.
15. H. Wang, L. Peh, and S. Malik, "Power-Driven Design of Router Microarchitectures in On-Chip Networks," Proc. 36th Ann. IEEE/ACM Int'l Symp. Microarchitecture (MICRO 36), IEEE CS Press, 2003, pp. 105-116.
16. H. Wang, L. Peh, and S. Malik, "A Power Model for Routers: Modeling Alpha 21364 and Infiniband Routers," IEEE Micro, vol. 23, no. 1, Jan.-Feb. 2003, pp. 26-35.
17. K. Rijpkema et al., "Trade-Offs in the Design of a Router with Both Guaranteed and Best-Effort Services for Networks on Chip," IEE Proc. Computers and Digital Techniques, vol. 150, no. 5, 2003, pp. 294-302.
18. P. Wolkotte et al., "An Energy-Efficient Reconfigurable Circuit-Switched Network-on-Chip," Proc. IEEE Int'l Parallel and Distributed Symp. (IPDS 05), IEEE CS Press, 2005, p. 155a.
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