Issue No. 05 - September/October (2007 vol. 27)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/MM.2007.90
Paul Gratz , The University of Texas at Austin
Changkyu Kim , Intel
Karthikeyan Sankaralingam , University of Wisconsin-Madison
Heather Hanson , IBM
Premkishore Shivakumar , The University of Texas at Austin
Stephen W. Keckler , The University of Texas at Austin
Doug Burger , The University of Texas at Austin
The TRIPS chip prototypes two networks on chip to demonstrate the viability of a routed interconnection fabric for memory and operand traffic. In a 170-million-transistor custom ASIC chip, these NoCs provide system performance within 28 percent of ideal noncontended networks at a cost of 20 percent of the die area. Our experience shows that NoCs are area- and complexity-efficient means of providing high-bandwidth, low-latency on-chip communication.
on-chip interconnection networks, multicore architectures, distributed architectures, packet-switching networks, communication, networking
S. W. Keckler et al., "On-Chip Interconnection Networks of the TRIPS Chip," in IEEE Micro, vol. 27, no. , pp. 41-50, 2007.