Issue No. 05 - September/October (2007 vol. 27)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/MM.2007.89
David Wentzlaff , Tilera
Patrick Griffin , Tilera
Henry Hoffmann , Tilera
Liewei Bao , Tilera
Bruce Edwards , Tilera
Carl Ramey , Tilera
Matthew Mattina , Tilera
Chyi-Chang Miao , Tilera
John F. Brown III , Tilera
Anant Agarwal , Tilera
iMesh, the Tile Processor Architecture's on-chip interconnection network, connects the multicore processor's tiles with five 2D mesh networks, each specialized for a different use. Taking advantage of the five networks, the c-based iLib interconnection library efficiently maps program communication across the on-chip interconnect. The Tile Processor's first implementation, the TILE64, contains 64 cores and can execute 192 billion 32-bit operations per second at 1 GHz.
MIMD processors, on-chip interconnection networks, multicore architectures, mesh networks, parallel architectures
B. Edwards et al., "On-Chip Interconnection Architecture of the Tile Processor," in IEEE Micro, vol. 27, no. , pp. 15-31, 2007.