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Issue No. 01 - January/February (2007 vol. 27)
ISSN: 0272-1732
pp: 12-25
Satish Narayanasamy , University of California, San Diego
Bruce Carneal , University of California, San Diego
Smruti Sarangi , University of Illinois, Urbana-Champaign
Josep Torrellas , University of Illinois, Urbana-Champaign
Brad Calder , University of California, San Diego, and Microsoft
Abhishek Tiwari , University of Illinois, Urbana-Champaign
ABSTRACT
Equipping processors with programmable hardware to patch design errors lets manufacturers release regular hardware patches, avoiding costly chip recalls and potentially speeding time to market. For each error detected, the manufacturer creates a fingerprint, which the customer uses to program the hardware. The hardware watches for error conditions; when they arise, it takes action to avoid the error.
INDEX TERMS
hardware errors, microarchitecture for fault-tolerance, design defects in real processors, processor errata analysis
CITATION
Satish Narayanasamy, Bruce Carneal, Smruti Sarangi, Josep Torrellas, Brad Calder, Abhishek Tiwari, "Patching Processor Design Errors with Programmable Hardware", IEEE Micro, vol. 27, no. , pp. 12-25, January/February 2007, doi:10.1109/MM.2007.19
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