Pages: pp. 8-9
Well, it's time for me to say good-bye! As my EIC tenure comes to an end with this final issue, I cannot help but pause briefly and think about the past four years. I was lucky to have the aid of a highly talented editorial board, an eminent advisory board, and an enthusiastic staff; together, we were able to make some positive changes to this premier magazine. When I took over in 2003, the IT industry was still reeling from the now-historic "dotcom bust." Events that brought change to the computer hardware business naturally affected things depending on that business—for example, technical publications relating to the computer industry, especially hardware-related literature. Change is always difficult, and usually inevitable—especially during hard times. But, with the support of the board members, we were able to change course for the better, building up Micro's image and quality while keeping pace with relevant new topics of interest to our readership. I am tremendously grateful to the computer architecture R&D community at large for the enthusiastic support I received as we tried out new ideas, themes, and columns. And, of course, the dedication of the editorial staff over the years is something I will remember and cherish.
Now, a brief look over the technical landscape of the past four years: What has changed since the beginning of 2003? As I took office at Micro, the frequency wars characteristic of single-core processor designs had barely started giving way to a new trend of multicore chips. Four years later, that trend is a firmly established fact of life, with vendors planning to support tens (if not hundreds) of computing threads on a single microprocessor chip within the next few years. The resulting impact on new-generation software and application enablement for multicore platforms is rejuvenating mature (yet somewhat dormant) fields—vectorization and parallelizing compilers, resource-aware operating-system task scheduling, and others.
Newer, technology- and environment-driven problems—such as variation-tolerant design, reliable design in the face of unreliable components, dynamic power, thermal and inductive noise management, and security-aware microarchitectures—have provided ample material for the research community. Some of the solutions are already beginning to creep into real designs. We have seen at least one bold new commercial design that has taken the step of including an on-chip, programmable microcontroller to monitor operating conditions (such as current, voltage, power, temperature, and performance) and take corrective actions to ensure adherence to strict, chip-level constraints such as power dissipation limits.
As the number of cores increases in the face of escalating process variability effects, managing physical constraints like power, voltage droops, and temperature will require complex, hierarchical feedback control systems—routinely architected as part of the overall system. Software (and firmware) will certainly play a big role in all of this, as chip architects try to reduce design complexity by adopting simpler, more power-efficient cores. Presilicon modeling challenges will force chip-level R&D folks to seek out new paradigms of analysis and prediction: Single-core, cycle-accurate, power-performance simulators are already giving way to full-system, multicore simulators—and that trend is likely to continue. Hardware emulators (FPGA-based, for example) offer promising new vehicles for future pre-product modeling and bring-up tasks.
Of course, there's also a lot more to anticipate than just general-purpose microprocessor chips and their enabling software. Special-purpose application areas, such as games, mobile communications, and multimedia, have spawned amazing growth in high-performance microprocessors that include specialized support in the form of accelerator subcores and other support engines. Emerging new applications in these and other areas are likely to drive the proliferation of a wide variety of ultra-power-efficient, high-performance processor chips that cater to specialized markets.
As Micro steps into the next four years, the possibilities are tremendous. It is my great pleasure and privilege to introduce our readers to the new Editor in Chief, Professor David H. Albonesi, of Cornell University, who will take over in January 2007. The very first issue in 2007 will be our annual Top Picks issue—now firmly a part of the Micro heritage. With the help of a fantastic program committee (which included Albonesi) we have finished the work of selecting for the issue the "top" papers from the computer architecture conferences of 2006. However, the hard work of overseeing the final product and ensuring timely publication remains ahead of us…and the new EIC is already gearing up to bring his talent and organizational skills to bear on the project! I could not have asked for a better or more competent person to rely upon during this transition. David Albonesi brings years of proven research and industry experience to the EIC position. I am absolutely certain that this great magazine will rise to spectacular heights of quality and appeal under his able leadership. Please continue to support the magazine through your subscriptions, contributed articles, and constructive feedback.
A word now about this year-end issue: Originally, we had planned it as a Hot Tutorials issue that would selectively present a few articles addressing emerging topics in a survey- cum-tutorial format. However, we did not receive enough good articles that would pass the magazine's review process. To allow more time for submissions, review, and revisions, we have postponed the Hot Tutorials issue to May–June 2007, and present instead a general issue with three very good technical articles. Pérez, Berry, and Temam describe a new workload sampling method that addresses warm-up corrections while preserving simulation speed at high accuracy. In the article by Unsal et al., we see a treatment of the important topic of variation-tolerant design; this is a survey paper of immediate interest to the microprocessor R&D community. Lastly, Balasubramonian et al. propose a novel approach to future processor design, in which the architect is aware of different wire (interconnect) characteristics—from the point of view of latency, bandwidth, and power—and builds in dynamic steering of data movements in a manner that optimizes performance at reduced energy cost. I hope you enjoy this year-end issue of Micro.
Editor in Chief