Issue No. 02 - March/April (2006 vol. 26)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/MM.2006.39
Chris H. Kim , University of Minnesota
Arijit Raychowdhury , Purdue University
Kaushik Roy , Purdue University
Amit Agarwal , Intel Corp.
Saibal Mukhopadhyay , Purdue University
Leakage current in the nanometer regime has become a significant portion of power dissipation in CMOS circuits as threshold voltage, channel length, and gate oxide thickness scale downward. Various techniques are available to reduce leakage power in high-performance systems.
leakage power reduction, nanoscale circuits, CMOS, technology scaling
Chris H. Kim, Arijit Raychowdhury, Kaushik Roy, Amit Agarwal, Saibal Mukhopadhyay, "Leakage Power Analysis and Reduction for Nanoscale Circuits", IEEE Micro, vol. 26, no. , pp. 68-80, March/April 2006, doi:10.1109/MM.2006.39