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Issue No. 02 - March/April (2006 vol. 26)
ISSN: 0272-1732
pp: 10-24
Takeshi Yamazaki , Sony Computer Entertainment
Yukio Watanabe , Toshiba
ABSTRACT
Eight synergistic processor units enable the Cell Broadband Engine's breakthrough performance. The SPU architecture implements a novel, pervasively data-parallel architecture combining scalar and SIMD processing on a wide data path. A large number of SPUs per chip provide high thread-level parallelism.
INDEX TERMS
synergistic processing, Cell Broadband Engine, multicore architecture
CITATION
Brian Flachs, Michael Gschwind, Takeshi Yamazaki, Martin Hopkins, H. Peter Hofstee, Yukio Watanabe, "Synergistic Processing in Cell's Multicore Architecture", IEEE Micro, vol. 26, no. , pp. 10-24, March/April 2006, doi:10.1109/MM.2006.41
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