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Issue No. 01 - January/February (2006 vol. 26)
ISSN: 0272-1732
pp: 80-91
Jose Renau , University of California at Santa Cruz
Karin Strauss , University of Illinois at Urbana-Champaign
Luis Ceze , University of Illinois at Urbana-Champaign
Wei Liu , University of Illinois at Urbana-Champaign
Smruti R. Sarangi , University of Illinois at Urbana-Champaign
James Tuck , University of Illinois at Urbana-Champaign
Josep Torrellas , University of Illinois at Urbana-Champaign
ABSTRACT
Chip multiprocessors with thread-level speculation have become the subject of intense research. This work refutes the claim that such a design is necessarily too energy inefficient. In addition, it proposes out-of-order task spawning to exploit more sources of speculative task-level parallelism.
INDEX TERMS
Thread-level speculation, chip multiprocessors, out-of-order task spawning
CITATION

L. Ceze et al., "Energy-Efficient Thread-Level Speculation," in IEEE Micro, vol. 26, no. , pp. 80-91, 2006.
doi:10.1109/MM.2006.11
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