Issue No. 01 - January/February (2006 vol. 26)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/MM.2006.25
Ronald D. Barnes , George Mason University
Shane Ryoo , University of Illinois, Urbana-Champaign
Wen-mei W. Hwu , University of Illinois, Urbana-Champaign
Multipass pipelining uses compile-time scheduling to exploit parallelism and persistent advance execution to achieve memory-latency tolerance, while maintaining the simplicity of an in-order design.
Flea-flicker, multipass pipelining, memory-latency tolerance, in-order design
S. Ryoo, R. D. Barnes and W. W. Hwu, "Tolerating Cache-Miss Latency with Multipass Pipelines," in IEEE Micro, vol. 26, no. , pp. 40-47, 2006.