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Issue No. 01 - January/February (2006 vol. 26)
ISSN: 0272-1732
pp: 40-47
Shane Ryoo , University of Illinois, Urbana-Champaign
Ronald D. Barnes , George Mason University
Wen-mei W. Hwu , University of Illinois, Urbana-Champaign
ABSTRACT
Multipass pipelining uses compile-time scheduling to exploit parallelism and persistent advance execution to achieve memory-latency tolerance, while maintaining the simplicity of an in-order design.
INDEX TERMS
Flea-flicker, multipass pipelining, memory-latency tolerance, in-order design
CITATION
Shane Ryoo, Ronald D. Barnes, Wen-mei W. Hwu, "Tolerating Cache-Miss Latency with Multipass Pipelines", IEEE Micro, vol. 26, no. , pp. 40-47, January/February 2006, doi:10.1109/MM.2006.25
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