Issue No. 01 - January/February (2006 vol. 26)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/MM.2006.1
Ibrahim Hur , IBM Corp. and The University of Texas at Austin
Calvin Lin , The University of Texas at Austin
Careful memory scheduling can increase memory bandwidth and overall system performance. We present a new memory scheduler that makes decisions based on the history of recently scheduled operations, providing two advantages: It can better reason about the delays associated with complex DRAM structure, and it can adapt to different observed workload.
Memory schedulers, memory bandwidth, processors, DRAM, IBM Power5
C. Lin and I. Hur, "Adaptive History-Based Memory Schedulers for Modern Processors," in IEEE Micro, vol. 26, no. , pp. 22-29, 2006.