Guest Editor's Introduction: Micro's Top Picks from Microarchitecture Conferences

Josep Torrellas, University of Illinois, Urbana-Champaign

Pages: pp. 8-9

With this special issue, IEEE Micro continues its yearly tradition of showcasing some of the most industry-relevant research presented at the top computer architecture conferences of the previous year. IEEE Micro's readership includes many busy computing professionals who, while interested in recent trends and advances in computer architecture, do not have the time to carefully follow the top computer architecture conferences where many such trends are taking shape. For these and many other readers, this special issue attempts to collect and summarize some of last year's most significant research contributions that might have the biggest impact on future industrial designs. IEEE Micro has defined impact in broad terms, to include both short- and long-term potential. Of course, the selection process has necessarily been imperfect, surely missing many excellent ideas. The guest editor and program committee feel, however, that the selected 13 papers represent a good cross-cutting snapshot of promising research advances.

Review process

Building on the experience of past years, Micro issued a call for extended abstracts of papers published at the top computer architecture conferences of 2005. The abstracts were limited to three pages and had to summarize the contribution and argue the relevance to industry. Based on this call, Micro received 80 submissions. A program committee made of reputable professionals who are active in the field and have first-hand experience in how research advances have impact in industry took the task of selecting the papers to include in the issue. The committee had the following 25 members, who came equally from industry and academia, and included many of the program chairs of the top computer architecture conferences of the previous year:

  • Santosh Abraham, Sun Microsystems
  • David Albonesi, Cornell University
  • Pradip Bose, IBM Corp.
  • Brad Calder, University of California, San Diego
  • Tom Conte, North Carolina State University
  • Pradip Dubey, Intel Corp.
  • Joel Emer, Intel Corp.
  • Phil Emma, IBM Corp.
  • Antonio Gonzalez, Universitat Politecnica de Catalunya and Intel Corp.
  • Rajiv Gupta, University of Arizona
  • Mark Hill, University of Wisconsin
  • Wen-mei Hwu, University of Illinois, Urbana-Champaign
  • Konrad Lai, Intel Corp.
  • Kathryn McKinley, University of Texas at Austin
  • Chuck Moore, Advanced Micro Devices
  • Jaime Moreno, IBM Corp.
  • Ronny Ronen, Intel Corp.
  • Kevin Rudd, Intel Corp.
  • John Shen, Intel Corp.
  • Balaram Sinharoy, IBM Corp.
  • Jim Smith, University of Wisconsin-Madison
  • Marc Tremblay, Sun Microsystems
  • Mateo Valero, Universitat Politecnica de Catalunya
  • Xiaodong Zhang, College of William and Mary
  • Victor Zyuban, IBM Corp.

Four committee members—typically two from industry and two from academia—reviewed each abstract; they were also encouraged to read the full-paper version. The large majority of the submissions had strong technical contributions; this was never in doubt, given that the papers had survived rigorous conference reviewing processes. The program committee was asked to evaluate the more subjective matter of potential industry impact. For that, the committee members relied on their experience and on spirited discussions before and during the program committee meeting. Unfortunately, such discussions and thoughts are hard to capture in the feedback form returned to the authors. The entire review process followed strict conflict-of-interest rules. At the program committee meeting in Chicago, the committee accepted 13 papers. The magazine's page limits forced us to leave out several very strong contributions.

The selected papers

The 13 articles in this year's Top Picks issue appear in the sidebar. They cover a wide spectrum of active research areas within computer architecture. About half of the contributions focus on obtaining higher performance, while the rest deal with programmability, security, fault tolerance, software debugging, energy or power efficiency, and temperature modeling.


We hope that you find these papers interesting and that they inspire you to read the original work and make some connections with design issues on which you are working. We also welcome your feedback on this year's Top Picks issue and any suggestions on how to improve this issue in future years.

2005 Micro Top Picks

Processor and memory architectures for high performance

  • "Efficient Runahead Execution: Power-Efficient Memory Latency Tolerance"
  • "Adaptive History-Based Memory Schedulers for Modern Processors"
  • "Scalable Load and Store Processing in Latency-Tolerant Processors"
  • "Tolerating Cache-Miss Latency with Multipass Pipelines"
  • "Wish Branches: Enabling Adaptive and Aggressive Predicated Execution"

Multiprocessing and multithreading

  • "Unbounded Transactional Memory"
  • "Coarse-Grain Coherence Tracking: RegionScout and Region Coherence Arrays"
  • "Energy-Efficient Thread-Level Speculation"

Security and hardware or software robustness

  • "Opportunistic Transient-Fault Detection"
  • "BugNet: Recording Application-Level Execution for Deterministic Replay Debugging"
  • "Architectures for Bit-Split String Scanning in Intrusion Detection"

Energy and temperature issues

  • "Dynamic-Compiler-Driven Control for Microprocessor Energy and Performance"
  • "Temperature-Aware On-Chip Networks"


This issue would not have been possible without the dedication of the members of the program committee, who donated many hours of their time reviewing the submissions. I acknowledge the support of IEEE Micro Editor-in-Chief Pradip Bose, and the IEEE Micro staff, especially Kimberly Banker, Janet Wilson, and Ed Zintel. I also thank University of Illinois researchers Wonsun Ahn, Wei Liu, and Radu Teodorescu, who made sure that the review process worked successfully. Finally, I would like to thank all the authors who submitted papers; every single submission represented an immense amount of thought and effort.

About the Authors

Josep Torrellas is a professor of computer science and Willett Faculty Scholar at the University of Illinois, Urbana-Champaign. He is also the chair of the IEEE Technical Committee on Computer Architecture (TCCA). His research interests include multiprocessor computer architecture, thread-level speculation, low-power design, reliability, and debuggability. Torrellas has a PhD in electrical engineering from Stanford University. He is a Fellow of the IEEE and a member of the ACM.
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