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Measuring the impact of microarchitectural ideas


Pages: pp. 5-6

Welcome to IEEE Micro's first issue of 2006. The editorial board and I are starting this year with our annual Top Picks issue. This is the third such annual collection of magazine-style adaptations of top-rated papers selected from the past year's computer architecture and design conferences. This year, Josep Torrellas (University of Illinois at Urbana-Champaign) chaired the Top Picks program committee; please refer to his guest editor's introduction for details about the rest of the program committee and the evaluation procedure, criteria, and so on. One of the major criteria we use in selecting from papers that are submitted for consideration is industry impact, that is, the potential of influencing future real product offerings in a tangible and significant manner.

However, determining the true impact of a newly published microarchitectural design idea, a novel evaluation methodology paper, or a comprehensive hardware-measurement-based analysis publication is always a big challenge. In a real design team, microarchitects (with collaborative help from presilicon modelers/analysts and postsilicon measurement-based analysts) are responsible for defining the high-level concepts that drive the later-stage detailed design and implementation of the microprocessor chip. Fundamental mistakes made at this concept phase can derail a project, resulting in late-stage unpleasant surprises. This can obviously lead to significant delays or even project cancellation, causing loss of financial opportunity and competitiveness. In the modern (late CMOS) design era, such unpleasant surprises are usually in the form of power, area, or verification budget overrun, although performance shortfalls continue to be a common form of such surprises. The problem of technology-related variability and the difficulty of accurate early stage assessment of power and verification complexity are the main factors that have significantly escalated the challenge of the modern microarchitect or designer. As such, microarchitecture research, which is targeted to influence a design microarchitect's next-generation concepts, often has the onerous task of trying to back up a new idea with sufficient evaluation depth and data. Hence, the development of efficient new presilicon evaluation methodologies (with acceptable levels of accuracy) are an essential part of leading-edge microarchitecture R&D. Lessons learned from accurate measurement and interpretation of data obtained from prior-generation systems and advance test chips are also a very important aspect of the input that influences the design microarchitect's decision process. As such, comprehensive measurement-based articles that build fundamental understanding are often of great impact to future design.

In some cases, a breakthrough new concept can yield considerable impact even before researchers can fully evaluate the idea with real workloads. Usually these are one of two categories:

  • an elegant new solution to a known problem that is no more complex than the most commonly used approach, and yet clearly achieves improved functionality; or
  • an entirely new feature, based on a simple concept that is easy to understand and would clearly improve a desired metric (like performance, power, or both) quite a bit, even though the exact numbers might not be immediately available or believable.

Admittedly, the description of these two categories implies an element of subjective judgment; in other words, it is hard to imagine that there would be universal and instant agreement among reviewers about things like novelty, complexity, and the potential benefit. However, I feel strongly about the need to look for such elegant new ideas, even if the published methodology of evaluation and the actual reported numbers are suspect. By the way, an example of the first category could be a new instruction fetch policy, combined with fetch-gating in a simultaneously multithreading processor that is of the same or lower complexity than a vanilla round-robin algorithm, and yet results in significant benefit in terms of performance and power. An example of the second category might be the concept of "silent" stores and the appropriate microarchitectural support to exploit it. (The astute reader will have noted that I conveniently chose a couple of examples that were published well before the start of the Top Picks theme issues!)

No matter how you try to define impact on real design, it is always going to be difficult to select papers that are of maximum impact potential. But, we hope that with an experienced and knowledgeable selection committee, the papers that are finally chosen through the review process are certainly among the most promising. Nonetheless, it is almost certain that each year we have made a few mistakes. In particular, I am sure that we have missed a key paper or two each year—ones that would eventually end up creating a major impact on the industry.

I hope you enjoy the current collection of Top Picks. And, I look forward to receiving your feedback. I am especially interested in your pointers to papers (published in conferences last year) that you would have expected to find in this theme issue, but did not. We wish all our readers a very happy new year!

Pradip Bose

Editor in Chief

IEEE Micro

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