Issue No. 06 - November/December (2005 vol. 25)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/MM.2005.107
Daniel Stasiak , STG at IBM in Austin, Texas
Rajat Chaudhry , STG at IBM in Austin, Texas
Dennis Cox , STG at IBM in Rochester, Minnesota
Stephen Posluszny , STG at IBM in Austin, Texas
Jim Warnock , STG at IBM in Yorktown Height, New York
Steve Weitzel , STG at IBM in Austin, Texas
Dieter Wendel , STG at IBM in Boeblingen, Germany
Michael Wang , STG at IBM in Austin, Texas
Power consumption is one of the major challenges in VLSI Design. Power constrained designs must attack power reduction with many techniques and need tools to accurately predict the power consumption to provide designers feedback on the efficiency of the power management logic. This paper presents the reduction techniques used, the methodology behind cycle accurate power estimation, and hardware measurements vs. power estimates correlation on the first generation CELL Processor.
Cell processor, low power consumption, VLSI, design methodology
D. Cox et al., "Cell Processor Low-Power Design Methodology," in IEEE Micro, vol. 25, no. , pp. 71-78, 2005.