The Community for Technology Leaders
Green Image
Issue No. 05 - September/October (2005 vol. 25)
ISSN: 0272-1732
pp: 52-62
Margaret Martonosi , Princeton University
Li-Shiuan Peh , Princeton University
Philo Juang , Princeton University
Douglas W. Clark , Princeton University
Qiang Wu , Princeton University
These techniques determine when to speed up a processor to reach performance targets and when to slow it down to save energy. They use dynamic voltage and frequency scaling to balance speed and avoid worst case frequency limitations for both multiple-clock-domain and chip multiprocessors.
Power performance management, dynamic voltage, frequency sealing, multiple-clock-domain, chip multiprocessors
Margaret Martonosi, Li-Shiuan Peh, Philo Juang, Douglas W. Clark, Qiang Wu, "Formal Control Techniques for Power-Performance Management", IEEE Micro, vol. 25, no. , pp. 52-62, September/October 2005, doi:10.1109/MM.2005.87
121 ms
(Ver 3.3 (11022016))