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Issue No. 05 - September/October (2005 vol. 25)
ISSN: 0272-1732
pp: 30-38
Toru Asano , IBM Engineering and Technology Services
Joel Silberman , IBM T.J. Watson Research Center
Sang H. Dhong , IBM Systems and Technology Group
Osamu Takahashi , IBM Systems and Technology Group
Michael White , IBM Systems and Technology Group
Scott Cottier , IBM T.J. Watson Research Center
Takaaki Nakazato , Toshiba Semiconductor Company
Atsushi Kawasumi , Toshiba Semiconductor Company
Hiroshi Yoshihara , Sony Computer Entertainment of America
The Synergistic Processor Element is a new architecture oriented for multimedia and streaming processing. In this architecture, the memory is not a cache but a private or scratch pad memory. Such a memory is simple and needs to be high-frequency and large space in low-power. This design uses an 11 fan-out of four (11F04), six-cycle, fully pipelined, embedded 256-Kbyte SRAM for this purpose. The design's memory is not one hard macro, but a group of custom macros physically distributed to optimize the pipeline.
11 fan-out of four, 11FO4, Cell processor, Synergistic Processor Element, multimedia processing, streaming processing, private memory, scratch pad memory

T. Asano et al., "Low-Power Design Approach of 11FO4 256-Kbyte Embedded SRAM for the Synergistic Processor Element of a Cell Processor," in IEEE Micro, vol. 25, no. , pp. 30-38, 2005.
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