Issue No. 05 - September/October (2005 vol. 25)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/MM.2005.89
Pradip Bose , IBM T.J. Watson Research Center
Kunio Uchiyama , Hitachi
Energy efficiency has been a key design constraint for microprocessor development teams since the late 1990s. The fundamental technological issues that have led to this point are quite well understood at this time by industry and academia. Although active (or dynamic) and passive (or standby) components of the net power equation are of concern, in recent years the latter (leakage) aspect of chip power has been escalating at a much faster rate than active power. In fact, as we write, leakage power has almost equaled active power in the total power breakdown of a typical microprocessor. This means that a 100 W chip in today's technology will be burning about 50 W with just power on and no program running! And, by the way, the highest-performance, multicore, server-class processors are already close to 200 W in maximum power consumption! This equates to power densities that are pretty much at the very edge of air-cooled systems. So, without investing in liquid-cooled systems and their corresponding packaging (at significantly higher cost), microprocessors at the high end, targeted for traditional air-cooled server boxes, are pretty much at the end of the road, without a major paradigm shift in design and/or packaging technology. In fact, such a basic paradigm shift has been in the works for a few years, with the introduction of IBM's dual-core Power4 chip in 2000, for example. The industry in general has recently made a clear shift toward lower frequency, multicore architectures for general-purpose high-performance microprocessors. Intel, AMD, and Sun Microsystems have all announced future product roadmaps that embrace the multicore paradigm.
Although such a shift has enabled design groups to keep going for a little while, the need for building power efficiency into the chip's noncore components continues unabated. Also, we recently have witnessed a trend toward finer levels of clock gating in all designs, and the increasing use of power-gated modes to reduce leakage. Academic research in low-power design techniques have evolved from lower-level issues related to the underlying device and circuit technologies to higher-level knobs available in the microarchitecture, architecture, and even the application and software layers. In addition to the established International Symposium on Low Power Electronic Design (ISLPED), other smaller conferences and workshops have emerged to highlight the latest research—especially at the architecture and design levels.
That's why IEEE Micro, in putting together a special issue on this important theme, decided to focus on two recently held (and relatively new) conferences: Cool Chips VIII, held April 2005 in Yokohama, Japan, and the fourth Annual Austin Conference on Energy Efficient Design (ACEED), held in March 2005 in Austin, Texas. (Both of these conferences are organized to have presentations by speakers, without formal proceedings of written papers.) As our readers might know, Cool Chips covers talks on exciting new processor products or test chips that have "low power" as a primary constraint; ACEED, on the other hand, deals more with general research topics related to this field. As technical program chairs for these two conferences, we then teamed up to organize this theme issue, after inviting an initial set of articles from selected speakers and then screening those further into a set of seven final choices after a due review process, per IEEE Micro guidelines. We initially received a total of 17 submissions (10 from Cool Chips and seven from ACEED). Each article received at least two independent reviews; many received more than two reviews. After receiving reviews by a given deadline, we guest editors tried to make initial recommendations. One of us (Pradip Bose, who is also editor-in-chief of IEEE Micro) then made the final decisions about inclusion in the theme issue.
Three of the six selected articles turned out to be related to the Cell processor developed by Sony, Toshiba, and IBM. As Peter Hofstee of IBM describes in the " First-Generation Cell Processor" sidebar, the Cell chip was designed as a heterogeneous, multicore system-on-chip, but using custom CMOS silicon-on-insulator technology, targeted to achieve leadership frequency and performance at affordable power, for the game market. The challenge of delivering such high performance at a power level that makes it possible to use the processor chip in a game console or set-top system, is understandably very steep.
In the article by Takahashi et al., the authors describe the power-aware design principles behind each of the synergistic processing element cores within the full chip. In their article, Maeda et al. deal with some of the challenging issues in the programming model, paying attention to power conservation issues in a real-time computing scenario. In the article by Asano et al., we find a treatment of the low-level design issues related to achieving a high-performance SRAM design (again, for the SPE cores within Cell) at low power.
The other three selections in this issue are research articles, reflecting some of the leading-edge academic research activities in the area of power-aware microarchitecture design. In their article on duration prediction, Isci et al. dwell on the problem of predicting the length (or time duration) of each distinct phase of an executing workload. In a setting where dynamic voltage/frequency scaling (DVFS) helps to manage power efficiently, the ability to accurately predict a phase's duration enables the precision deployment of the underlying voltage change mechanism at a low overhead cost. In the article on formal control techniques, Wu et al. touch on a topic that is of significant current interest within the field of energy-efficient design: on-chip adaptive control techniques and algorithms, an area that has received considerable coverage in recent academic research, as a basic mechanism to manage power in the presence of changing workload demands. In this article, the authors address the formal control-theoretic aspects of such mechanisms, pointing the community toward an era of mathematically provable, robust control algorithms.
Finally, the article by Marculescu et al. touches on a topic of increasing importance to the chip design community: that of uncertainty in design caused by the increased variability and failure rates of component devices and building blocks. How this emerging new constraint interplays with the now well-known constraint of power dissipation limits is the interesting subject of this article.
We hope you enjoy this theme issue on energy-efficient design. We would like to thank all the anonymous reviewers who helped us select this excellent collection of articles from two very relevant and interesting conferences. We are also grateful to all the authors who took the time and effort to submit written versions of their original talks to this special issue.
Kunio Uchiyama is a senior chief researcher in Hitachi's Central Research Laboratory, where he is responsible for the research and development of microprocessors and SoCs. His interests include microprocessors, SoC architecture, and design automation tools. Uchiyama has a PhD in advanced applied electronics from the Tokyo Institute of Technology. He was awarded the Japanese national Medal of Honor with Purple Ribbon, and is a senior member of the IEEE.
Pradip Bose is a research staff member and manager at the IBM T.J. Watson Research Center; he is also editor in chief of IEEE Micro. His research interests include high-performance computer architectures, power- and reliability-aware design, and computer-aided design. Bose has a PhD in electrical and computer engineering from the University of Illinois, Urbana-Champaign. He is a senior member of the IEEE and the IEEE Computer Society, and a member of the ACM.