Issue No. 04 - July/August (2005 vol. 25)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/MM.2005.64
Feipei Lai , National Taiwan University
Yen-Jen Chang , National Chung-Hsing University
A low-power cache has become essential in many applications, but cache accesses contribute significantly to a chip's total power consumption. Because most bit values read from the cache are 0s, the authors introduce a dynamic zero-sensitivity (DZS) scheme that reduces average cache power consumption by preventing bitlines from discharging in reading a 0.
Cache, Dynamic zero-sensitivity, Bitlines, DZS, Power reduction
Feipei Lai, Yen-Jen Chang, "Dynamic Zero-Sensitivity Scheme for Low-Power Cache Memories", IEEE Micro, vol. 25, no. , pp. 20-32, July/August 2005, doi:10.1109/MM.2005.64