Pages: pp. 5-6
In the last (May-June) issue of IEEE Micro, I projected a future of "integrated microarchitectures." Allow me to recap and further consolidate that view.
High-end, server-class microprocessor chips will begin to look like system-on-chip (SoC) designs, with the following on-chip heterogeneous elements:
The resulting presilicon modeling challenge in the setting of this late CMOS design era is quite mind-boggling. Early-stage simulators that (micro) architects rely upon clearly need to do much, much more—now and in the future—than single-core analysis of cycles per instruction (CPI). Transitioning to an acceptably fast and accurate multicore simulation framework is only a small part of the problem. The modeling toolkit must also have integrated power, temperature, and reliability analysis models. And, while all of these augmentations complicate and slow simulator speed significantly, future workloads keep becoming bigger, of course. Many R&D groups are currently making the transition to full-system, execution-driven simulators to pursue the research agenda for next-generation computer architectures. However, the problems of simulation speed, complexity, debugging, and maintenance are not easy. Parallelizing multiprocessor-system simulators to take advantage of next-generation parallel machines is in itself a research area that the performance evaluation and simulation community has pursued for quite some time; but, in terms of practical solutions, this task still remains somewhat elusive.
Invariably, I feel we will face at least a temporary phase, where architects must mix presilicon simulation and evaluation methods with statistical and analytical components. Chip-level microarchitects will continue to depend on models to help make fundamental early-stage decisions. But difficulties in detailed cycle-accurate integrated modeling will force lead architects, designers, and researchers to resort to more fundamental modes of reasoning with simplified, abstract analytical, and statistical formalisms. Core-level, cycle-accurate pipeline timing models are likely to become less essential; appropriate abstractions of those models will arise to work with more detailed models of noncore elements, such as pipelined cache hierarchy, interconnect network, and so on. And, even these latter "detailed" models will probably not be trace- or execution-driven simulators; scalability and speed issues will dictate the use of statistical and analytical shortcuts embedded within hybrid (analytical-simulation) modeling toolkits. If representative workload sampling is an issue today, its importance will increase at least tenfold in the next five years.
Validation of new-generation presilicon analysis models will of course also be a much greater challenge than in the past. It is not just about making sure CPI projections are within acceptable levels of accuracy. Such models must accurately project the effects of complex trade-offs between power, temperature, reliability, and performance within the multicore design paradigm, such that later stages of design do not encounter project-threatening surprises. The interdisciplinary skills needed by the modeling team and the uncertainties posed by technology (device) models of the future make the challenge much steeper than before.
The microprocessor R&D community (especially in the architecture community) has not committed enough resources to the modeling and workload characterization discipline. As a result, we have not trained enough people and are therefore not positioned well to face future modeling challenges. I am very glad to note, however, that the architecture community has invested in two new conferences (the International Symposium on Performance Analysis of Systems and Software, or ISPASS, which is now a few years old; and the IEEE International Symposium on Workload Characterization, or IISWC, which is starting up this year). These, of course, have grown out of successful past workshops. I sincerely urge the architecture R&D community to build up these new conferences by encouraging new work in this topic area. The software and application (workload) view that building up this area forces us to adopt will be extremely beneficial in guiding the community toward future cost-effective, chip-level microarchitectures.
IEEE Micro would like to encourage and support an increased awareness of and emphasis on presilicon modeling within the architecture community. The editorial board, our advisors, and I are looking for quality articles and special issue proposals in this key area. Please do send me your comments and views on this general subject. We depend on such feedback from all our valued readers, to make sure we are making appropriate adjustments to the scope of coverage, in keeping with changes in the field.
This particular issue of Micro is a nontheme, general offering, with a collection of articles that address various aspects of microprocessor and microprocessor-based system design. Research papers by Zhu et al. and Chang et al. deal with power reduction problems in processor cores and caches. Beecroft et al. present a particular interprocessor communication network designed to optimize performance in systems constructed from standard server building blocks. Papers by Wu et al. and Akhbarizadeh et al. cover design issues and ideas related to ternary content-addressable memories (TCAMs): hardware devices for fast routing lookups in a network processing context.
We have two exciting new theme issues coming up next. The September-October issue will cover low-power processors and technology, and the November-December issue will cover the emerging new topic area of reliability-aware microarchitectures. We are moving the usual year-end Micro Top Picks issue to early 2006 to give the review committee more time to consider all of the papers published in recent architecture conferences.