Issue No. 04 - July/August (2005 vol. 25)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/MM.2005.74
<em>IEEE Micro</em> editor in chief Pradip Bose writes that in a future of "integrated microarchitectures," high-end, server-class microprocessor chips will begin to look like system-on-chip designs with multiple processor cores, special-purpose accelerators invoked on demand, and a scalable on-chip interconnection network, among other on-chip heterogeneous elements. The resulting presilicon modeling challenges in the setting of this late CMOS design era are quite mind-boggling.
Integrated microarchitectures, special purpose accelerators, scalable on-chip interconnection network, presilicon modeling, CMOS
P. Bose, "Presilicon modeling: challenges in the late CMOS era," in IEEE Micro, vol. 25, no. , pp. 5-6, 2005.