Issue No. 01 - January/February (2005 vol. 25)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/MM.2005.20
Thomas H. Dunigan Jr. , Oak Ridge National Laboratory
Jeffrey S. Vetter , Oak Ridge National Laboratory
James B. White III , Oak Ridge National Laboratory
Patrick H. Worley , Oak Ridge National Laboratory
The Cray X1 supercomputer's distributed shared memory presents a 64-bit global address space that is directly addressable from every MSP with an interconnect bandwidth per computation rate of 1 byte/flop. Our results show that this high bandwidth and low latency for remote memory accesses translate into improved application performance on important applications.
P. H. Worley, T. H. Dunigan Jr., J. S. Vetter and J. B. White III, "Performance Evaluation of the Cray X1 Distributed Shared-Memory Architecture," in IEEE Micro, vol. 25, no. , pp. 30-40, 2005.