, University of Massachusetts, Amherst Lancaster University, UK
, Bell Laboratories, Lucent Technologies
Pages: pp. 8-9
Hot Interconnects is an annual conference that specializes in state-of-the-art hardware and software architectures, and implementations of interconnection networks of all scales, ranging from on-chip, processor-memory interconnects to wide-area networks. It is the event where the high-performance computing and high-speed networking communities meet, and has a wide attendance both from industry and academia. Hot Interconnects 12 convened from 25 to 27 August 2004 at Stanford University; it included two days of paper sessions and one day of tutorials. Sponsored by the IEEE Computer Society Technical Committee on Microprocessors and Microcomputers, Hot Interconnects also has technical cosponsorship from the IEEE Communications Society Technical Committees on High-Speed Networking and Communications Switching and Routing.
In his keynote address, Nick McKeown of Stanford University argued that the industry should revisit some fundamental assumptions about the buffer sizes used in TCP/IP networks. In another keynote, Jonathan Turner of Washington University in St. Louis spoke about a motivation and strategy for network virtualization.
Researchers presented 15 papers; we selected the articles included in this issue of IEEE Micro on the basis of the highest reviewer ratings, feedback from conference participants, and an overall match with the IEEE Micro profile.
The first article focuses on intersystem interconnects. Krishnan and Mayhew address the topic of congestion control in advanced switching interconnects (ASI). The ASI architecture is based on PCI Express and shares the same physical and link layers, but it provides additional capabilities for multiprocessing and peer-to-peer computing. This article introduces and evaluates a localized congestion control mechanism for such systems. PCI Express is also the focus of a second article by Liu et al. which evaluates the performance of Infiniband host communication adapters with PCI Express. Results indicate that PCI Express brings significant performance improvements over that of PCI X, both in terms of throughput and latency.
A second set of articles focuses on interconnects for large-scale multiprocessors. Dunnigan et al. evaluate the performance of the Cray X1's distributed shared-memory architecture through extensive benchmarking simulations. Results indicate that this interconnect's high bandwidth and low latency significantly improve the performance of important applications. In their article, Kodi and Louri propose an optical interconnection network for scalable, distributed, shared-memory multiprocessors. As bandwidth requirements between processors increase, optical interconnects have the potential to break the scalability bottlenecks and provide high throughput, low latency, and low power consumption. The authors base the architecture they describe on a hierarchical network with optical links between groups of processors.
A third set of articles relates to the issue of security in data networks. Intrusion detection systems, virus scanners, and security subsystems require the deep inspection of packet contents. Such functions require real-time operation at very high speed and pose several challenges both in terms of algorithm and hardware design. Yu and Katz (who received the best paper award for Hot Interconnects 12) address the problem of multimatch packet classification, in which multiple classification rules can match each packet. They present a solution based on ternary content-addressable memories (TCAMs) that can produce results with just one TCAM and one SRAM lookup per packet, and approximately 10 times fewer memory lookups than a pure software approach. Madhusudan and Lockwood describe a hardware-based intrusion detection system that provides low reaction time and high throughput at low cost. The article presents several algorithms used in the system and describes a functional prototype based on an FPGA platform.
The article by Arekapudi et al. is on scalable switch design using the load-balanced architecture. The load-balanced switch is based on a space-memory-space interconnect in which the first stage load balances traffic across several middle-stage memories; the third stage delivers packets to their final destination. The article describes an instantiation of this architecture based on an optical switch fabric; it also presents an algorithm for reconfiguring the fabric in hardware.
As the program cochairs and tutorial organizers, we thank several individuals for their help in making Hot Interconnects 12 a success. Brian Lyles and Anne Watters served as general cochairs of the conference. Fabrizio Petrini organized the panels. Liz Rogers served as both the local chair and webmaster. The conference steering committee included Daniel Pitt, Hasan Alkhatib, Allen Baum, Glen Langdon, Mark Laubach, John Lockwood, and Bryan Lyles. Thanks are also due to the program committee for its thorough reviews and detailed comments that helped authors improve their papers. Finally, we thank Janet Wilson and Ed Zintel of the IEEE Computer Society for making our job as guest editors as easy as possible. Hot Interconnects 13 will be held 17 to 19 August 2005. Once again, the conference will be held on the campus of Stanford University, immediately after Hot Chips 16. For more information, visit the Hot Interconnects website at www.hoti.org.