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Welcome to IEEE Micro's first issue of 2005. Like last year, we begin with a theme issue on Hot Interconnects. In addition to this main theme, the issue also contains two other important articles dealing with mainstream microprocessor architectures.

In my message in September-October 2004, I wrote about the balance between computation and communication, and how that must change to enable scalable performance growth across evolving system architecture paradigms and the underlying technologies. In fact, as general-purpose microprocessors evolve into multicore chips, the on-chip interconnect will become a focal point of attention for architects, designers, and chip-level integrators. The attention will not arise from performance and scalability issues alone. The power consumed by the on-chip interconnect becomes an increasing fraction of the total power consumed by the chip. Increasing on-chip current densities could also lead to significantly higher hard and intermittent failures caused by effects like electromigration. As such, power-efficient, reliable on-chip interconnect design will become a key element of microprocessor design in future generations.

In general, the trend toward multicore architectures is naturally pointing the processor R&D community toward reexamining system-level architecture and design issues in the context of chip-level latency and bandwidth expectations. In presilicon modeling, as in design, the emphasis is shifting away from core-specific microarchitecture definition and trade-off analysis to chip-level issues. And these issues span much more than the traditional focus on cycles per instruction and processor frequency. Design for yield and manufacturability, power efficiency, lifetime reliability, and soft-error tolerance are examples of new considerations that are becoming routine even during the microarchitectural definition of the new-generation microprocessor chip. Power and complexity constraints are driving designers to return to simpler, lower-frequency processor cores, but this is what makes the on-chip interconnect and memory hierarchy design much more challenging.

Although today's chip designer stands to learn much from the experiences and knowledge gained by yesterday's system-level multiprocessor architect, it is the blend of understanding between today's unique technology trends, system architecture trade-offs, and VLSI design methods and tools that will make the competitive difference for future products. The challenge in a nutshell: Create the right balance between computation, storage, and interconnect resources for a target application mix and scale that balance point appropriately and in tune with trends in technology and applications. That's easier said than done, especially when the "right balance" means so much more than older, performance-centric viewpoints.

Micro ended 2004 with our second year-end Top Picks issue. As before, it was difficult if not impossible to be right in making sure we chose the very best industry-relevant architecture conference papers from last year for that issue. In fact, the editorial board and I continue to look for the best new ideas and analysis papers that are relevant to the design of future systems. Branch prediction and cache prefetch algorithms are well-trodden topics in the computer architecture literature. As such, new ideas and breakthroughs in these areas are difficult to come by; so the bar is often set higher in reviewers' minds.

The two additional papers in this issue (by Nesbit and Smith, and Falcon et al.) therefore deserve special attention. We liked these ideas (first published in recent computer architecture conferences) and made a special effort to bring them to the attention of the IEEE Micro readership in this issue through magazine-style renditions.

We wish all our readers a very happy new year and hope you enjoy this issue of IEEE Micro.

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