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Issue No. 06 - November/December (2004 vol. 24)
ISSN: 0272-1732
pp: 118-127
Charles R. Moore , The University of Texas at Austin
Stephen W. Keckler , The University of Texas at Austin
Rajagopalan Desikan , The University of Texas at Austin
Doug Burger , The University of Texas at Austin
Simha Sethumadhavan , The University of Texas at Austin
ABSTRACT
Power is a major problem for scaling the hardware needed to support memory disambiguation in future out-of-order architectures. In current machines, the traditional detection of memory ordering violations requires frequent associative searches of state proportional to the instruction window size. A new class of solutions yields an order-of-magnitude reduction in the energy required to properly order loads and stores for windows of hundreds to thousands of in-flight instructions.
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CITATION
Charles R. Moore, Stephen W. Keckler, Rajagopalan Desikan, Doug Burger, Simha Sethumadhavan, "Scalable Hardware Memory Disambiguation for High-ILP Processors", IEEE Micro, vol. 24, no. , pp. 118-127, November/December 2004, doi:10.1109/MM.2004.87
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