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Issue No. 06 - November/December (2004 vol. 24)
ISSN: 0272-1732
pp: 84-90
Steve Gerding , Massachusetts Institute of Technology
Brian Pharris , Massachusetts Institute of Technology
Jared Casper , Massachusetts Institute of Technology
Ronny Krashinsky , Massachusetts Institute of Technology
Mark Hampton , Massachusetts Institute of Technology
Christopher Batten , Massachusetts Institute of Technology
Krste Asanovic , Massachusetts Institute of Technology
ABSTRACT
The vector-thread (VT) architecture supports a seamless intermingling of vector and multithreaded computation to flexibly and compactly encode application parallelism and locality. VT processors exploit this encoding to provide high performance with low power and small area.
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CITATION
Steve Gerding, Brian Pharris, Jared Casper, Ronny Krashinsky, Mark Hampton, Christopher Batten, Krste Asanovic, "The Vector-Thread Architecture", IEEE Micro, vol. 24, no. , pp. 84-90, November/December 2004, doi:10.1109/MM.2004.90
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