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Issue No. 06 - November/December (2004 vol. 24)
ISSN: 0272-1732
pp: 62-73
Srikanth T. Srinivasan , Intel Microprocessor Technology Labs
Ravi Rajwar , Intel Microprocessor Technology Labs
Haitham Akkary , Intel Microprocessor Technology Labs
Amit Gandhi , Portland State University
Michael Upton , Intel Microprocessor Technology Labs
Continual flow pipelines let a processor core sustain a very large and adaptive instruction window while keeping its scheduler and register file small. The resulting improved cache efficiency, resource decoupling, and look-ahead capability enable many such cores to reside on a single chip for high throughput while enabling high single-thread performance.

R. Rajwar, H. Akkary, S. T. Srinivasan, A. Gandhi and M. Upton, "Continual Flow Pipelines: Achieving Resource-Efficient Latency Tolerance," in IEEE Micro, vol. 24, no. , pp. 62-73, 2004.
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