Issue No. 06 - November/December (2004 vol. 24)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/MM.2004.86
Christopher T. Weaver , Intel
Joel Emer , Intel
Shubhendu S. Mukherjee , Intel
Steven K. Reinhardt , University of Michigan
Unlike traditional approaches, which focus on detecting and recovering from faults, the techniques introduced here reduce the probability that a fault will cause a declared error. the first approach reduces the time instructions sit in vulnerable storage structures. The second avoids declaring errors on benign faults. Applying these techniques to a microprocessor instruction queue significantly reduces its error rate with only minor performance degradation.
S. S. Mukherjee, S. K. Reinhardt, C. T. Weaver and J. Emer, "Reducing the Soft-Error Rate of a High-Performance Microprocessor," in IEEE Micro, vol. 24, no. , pp. 30-37, 2004.