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TABLE OF CONTENTS
Issue No. 06 - November/December (vol. 24)
ISSN: 0272-1732
Editor-in-Chief's Message
Micro Economics
Micro's Top Picks from Microarchitecture Conferences

Razor: Circuit-Level Correction of Timing Errors for Low-Power Operation (Abstract)

Seokwoo Lee , University of Michigan
David Blaauw , University of Michigan
Nam Sung Kim , Intel Corp.
Todd Austin , University of Michigan
Dan Ernst , University of Michigan
Shidhartha Das , University of Michigan
Trevor Mudge , University of Michigan
Kriszti? Flautner , ARM Limited
pp. 10-20

Fingerprinting: Bounding Soft-Error-Detection Latency and Bandwidth (Abstract)

Jangwoo Kim , Carnegie Mellon University
James C. Hoe , Carnegie Mellon University
Andreas G. Nowatzyk , Carnegie Mellon University
Jared C. Smolens , Carnegie Mellon University
Brian T. Gold , Carnegie Mellon University
Babak Falsafi , Carnegie Mellon University
pp. 22-29

Performance-Directed Energy Management for Storage Systems (Abstract)

Xiaodong Li , University of Illinois at Urbana-Champaign
Pin Zhou , University of Illinois at Urbana-Champaign
Zhenmin Li , University of Illinois at Urbana-Champaign
Sarita V. Adve , University of Illinois at Urbana-Champaign
Sanjeev Kumar , Intel Laboratories
Yuanyuan Zhou , University of Illinois at Urbana-Champaign
pp. 38-49

iWatcher: Simple, General Architectural Support for Software Debugging (Abstract)

Feng Qin , University of Illinois at Urbana-Champaign
Pin Zhou , University of Illinois at Urbana-Champaign
Yuanyuan Zhou , University of Illinois at Urbana-Champaign
Josep Torrellas , University of Illinois at Urbana-Champaign
Wei Liu , University of Illinois at Urbana-Champaign
pp. 50-56

Interaction Cost: For When Event Counts Just Don't Add Up (Abstract)

Mark D. Hill , University of Wisconsin at Madison
Rastislav , University of California at Berkeley
Brian A. Fields , University of California at Berkeley
pp. 57-61

Continual Flow Pipelines: Achieving Resource-Efficient Latency Tolerance (Abstract)

Ravi Rajwar , Intel Microprocessor Technology Labs
Haitham Akkary , Intel Microprocessor Technology Labs
Srikanth T. Srinivasan , Intel Microprocessor Technology Labs
Amit Gandhi , Portland State University
Michael Upton , Intel Microprocessor Technology Labs
pp. 62-73

The Vector-Thread Architecture (Abstract)

Steve Gerding , Massachusetts Institute of Technology
Brian Pharris , Massachusetts Institute of Technology
Jared Casper , Massachusetts Institute of Technology
Ronny Krashinsky , Massachusetts Institute of Technology
Mark Hampton , Massachusetts Institute of Technology
Christopher Batten , Massachusetts Institute of Technology
Krste Asanovic , Massachusetts Institute of Technology
pp. 84-90

Transactional Coherence and Consistency: Simplifying Parallel Hardware and Software (Abstract)

Michael Chen , Stanford University
Vicky Wong , Stanford University
Lance Hammond , Stanford University
Christos Kozyrakis , Stanford University
Kunle Olukotun , Stanford University
Brian D. Carlstrom , Stanford University
pp. 92-103

Speculative Incoherent Cache Protocols (Abstract)

Jichuan Chang , University of Wisconsin-Madison
Doug Burger , The University of Texas at Austin
Jaehyuk Huh , The University of Texas at Austin
Gurindar S. Sohi , University of Wisconsin-Madison
pp. 104-109

Memory Ordering: A Value-Based Approach (Abstract)

Mikko H. Lipasti , University of Wisconsin
Harold W. Cain , IBM Research
pp. 110-117

Scalable Hardware Memory Disambiguation for High-ILP Processors (Abstract)

Charles R. Moore , The University of Texas at Austin
Stephen W. Keckler , The University of Texas at Austin
Rajagopalan Desikan , The University of Texas at Austin
Doug Burger , The University of Texas at Austin
Simha Sethumadhavan , The University of Texas at Austin
pp. 118-127
Departments

Micro News (HTML)

pp. 129

Micro Review: More on old themes (HTML)

Richard Mateosian , xrm@pacbell.net
pp. 133-134

2004 Annual Index (HTML)

pp. 135-144
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