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Issue No. 05 - September/October (2004 vol. 24)
ISSN: 0272-1732
pp: 10-18
Thomas Bod? , Xelerated
Jakob Carlstr? , Xelerated
ABSTRACT
The packet instruction set computer (PISC) architecture is a synchronous dataflow architecture developed for network processors. It uses a deep pipeline that contains two types of processing elements: PISC processors, which perform programmable data manipulation, and I/O processors, which provide access to shared resources such as look-up table memory, hardware accelerators, or coprocessors.
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CITATION
Thomas Bod?, Jakob Carlstr?, "Synchronous Dataflow Architecture for Network Processors", IEEE Micro, vol. 24, no. , pp. 10-18, September/October 2004, doi:10.1109/MM.2004.57
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