Issue No.05 - September/October (2004 vol.24)
Jakob Carlstr? , Xelerated
Thomas Bod? , Xelerated
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/MM.2004.57
The packet instruction set computer (PISC) architecture is a synchronous dataflow architecture developed for network processors. It uses a deep pipeline that contains two types of processing elements: PISC processors, which perform programmable data manipulation, and I/O processors, which provide access to shared resources such as look-up table memory, hardware accelerators, or coprocessors.
Jakob Carlstr?, Thomas Bod?, "Synchronous Dataflow Architecture for Network Processors", IEEE Micro, vol.24, no. 5, pp. 10-18, September/October 2004, doi:10.1109/MM.2004.57