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Issue No. 04 - July/August (2004 vol. 24)
ISSN: 0272-1732
pp: 33-41
Taeweon Suh , Georgia Institute of Technology
Hsien-Hsin S. Lee , Georgia Institute of Technology
Douglas M. Blough , Georgia Institute of Technology
This systematic methodology maintains cache coherency in a heterogeneous shared-memory multiprocessor system on a chip. It works with any combination of processors that support any invalidation-based protocol, and experiments have demonstrated up to a 51 percent performance improvement, compared to a pure software solution.

D. M. Blough, H. S. Lee and T. Suh, "Integrating Cache Coherence Protocols for Heterogeneous Multiprocessor Systems, Part 1," in IEEE Micro, vol. 24, no. , pp. 33-41, 2004.
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