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Issue No. 06 - November/December (2003 vol. 23)
ISSN: 0272-1732
pp: 70-75
Todd Austin , University of Michigan
Steven K. Reinhardt , Intel, University of Michigan
Christopher T. Weaver , Intel, University of Michigan
Joel Emer , Intel
ABSTRACT
<p>Processor designers need accurate estimates of soft-error rates early in the design cycle to make appropriate cost-reliability tradeoffs. Here, the authors present a method for estimating the architectural vulnerability factor—the probability that a fault in a particular structure will result in an error.</p>
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CITATION
Todd Austin, Steven K. Reinhardt, Christopher T. Weaver, Joel Emer, Shubhendu S. Mukherjee, "Measuring Architectural Vulnerability Factors", IEEE Micro, vol. 23, no. , pp. 70-75, November/December 2003, doi:10.1109/MM.2003.1261389
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