Issue No. 06 - November/December (2003 vol. 23)
Shubhendu S. Mukherjee , Intel
Christopher T. Weaver , Intel, University of Michigan
Joel Emer , Intel
Steven K. Reinhardt , Intel, University of Michigan
Todd Austin , University of Michigan
<p>Processor designers need accurate estimates of soft-error rates early in the design cycle to make appropriate cost-reliability tradeoffs. Here, the authors present a method for estimating the architectural vulnerability factor—the probability that a fault in a particular structure will result in an error.</p>
T. Austin, S. K. Reinhardt, C. T. Weaver, J. Emer and S. S. Mukherjee, "Measuring Architectural Vulnerability Factors," in IEEE Micro, vol. 23, no. , pp. 70-75, 2003.