The Community for Technology Leaders
Green Image
TABLE OF CONTENTS
Issue No. 06 - November/December (vol. 23)
ISSN: 0272-1732

Exploiting ILP, TLP, and DLP with the polymorphous trips architecture (Abstract)

K. Sankaralingam , Texas Univ., Austin, TX, USA
R. Nagarajan , Texas Univ., Austin, TX, USA
Haiming Liu , Texas Univ., Austin, TX, USA
Changkyu Kim , Texas Univ., Austin, TX, USA
Jaehyuk Huh , Texas Univ., Austin, TX, USA
D. Burger , Texas Univ., Austin, TX, USA
S.W. Keckler , Texas Univ., Austin, TX, USA
C. Moore , Texas Univ., Austin, TX, USA
pp. 46-51
Columns and Departments

Letters (HTML)

pp. 5
Features

Guest Editors' Introduction: Micro's Top Picks from Microarchitecture Conferences (HTML)

Charles Moore , The University of Texas at Austin
Ruby B. Lee , Princeton University
Pradip Bose , IBM T.J. Watson Research
pp. 8-10

Checkpoint Processing and Recovery: An Efficient, Scalable Alternative to Reorder Buffers (Abstract)

Haitham Akkary , Portland State University
Ravi Rajwar , Intel Microarchitecture Research Lab
Srikanth T. Srinivasan , Intel Microarchitecture Research Lab
pp. 11-19

Runahead Execution: An Effective Alternative to Large Instruction Windows (Abstract)

Yale N. Patt , The University of Texas at Austin
Chris Wilkerson , Intel Microarchitecture Research Lab
Onur Mutlu , The University of Texas at Austin
Jared Stark , Intel Microarchitecture Research Lab
pp. 20-25

Scalable Vector Processors for Embedded Systems (Abstract)

David A. Patterson , University of California at Berkeley
Christoforos E. Kozyrakis , Stanford University
pp. 36-45

Exploiting ILP, TLP, and DLP with the Polymorphous TRIPS Architecture (Abstract)

Jaehyuk Huh , The University of Texas at Austin
Charles Moore , The University of Texas at Austin
Changkyu Kim , The University of Texas at Austin
Ramadass Nagarajan , The University of Texas at Austin
Karthikeyan Sankaralingam , The University of Texas at Austin
Stephen W. Keckler , The University of Texas at Austin
Doug Burger , The University of Texas at Austin
Haiming Liu , The University of Texas at Austin
pp. 46-51

Temperature-Aware Computer Systems: Opportunities and Challenges (Abstract)

Mircea R. Stan , University of Virginia
Kevin Skadron , University of Virginia
Wei Huang , University of Virginia
David Tarjan , University of Virginia
Sivakumar Velusamy , University of Virginia
Karthik Sankaranarayanan , University of Virginia
pp. 52-61

Dynamic Frequency and Voltage Scaling for a Multiple-Clock-Domain Microprocessor (Abstract)

Sandhya Dwarkadas , University of Rochester
Greg Semeraro , Rochester Institute of Technology
Steven G. Dropsho , University of Rochester
David H. Albonesi , University of Rochester
Michael L. Scott , University of Rochester
pp. 62-68

Measuring Architectural Vulnerability Factors (Abstract)

Todd Austin , University of Michigan
Steven K. Reinhardt , Intel, University of Michigan
Christopher T. Weaver , Intel, University of Michigan
Joel Emer , Intel
pp. 70-75

Transient-Fault Recovery for Chip Multiprocessors (Abstract)

Irith Pomeranz , Purdue University
Mohamed A. Gomaa , Purdue University
T. N. Vijaykumar , Purdue University
Chad Scarbrough , Purdue University
pp. 76-83

Discovering and Exploiting Program Phases (Abstract)

Timothy Sherwood , University of California at Santa Barbara
Greg Hamerly , University of California at San Diego
Brad Calder , University of California at San Diego
Suleyman Sair , North Carolina State University
Erez Perelman , University of California at San Diego
pp. 84-93

Addressing Workload Variability in Architectural Simulations (Abstract)

Alaa R. Alameldeen , University of Wisconsin-Madison
David A. Wood , University of Wisconsin-Madison
pp. 94-98

Nonuniform Cache Architectures for Wire-Delay Dominated On-Chip Caches (Abstract)

Stephen W. Keckler , The University of Texas at Austin
Changkyu Kim , The University of Texas at Austin
Doug Burger , The University of Texas at Austin
pp. 99-107

Token Coherence: A New Framework for Shared-Memory Multiprocessors (Abstract)

Milo M.K. Martin , University of Wisconsin-Madison
Mark D. Hill , University of Wisconsin-Madison
David A. Wood , University of Wisconsin-Madison
pp. 108-116

Transactional Execution: Toward Reliable, High-Performance Multithreading (Abstract)

James Goodman , University of Auckland
Ravi Rajwar , Intel Microarchitecture Research Lab
pp. 117-125

Speculative Synchronization: Programmability and Performance for Parallel Codes (Abstract)

Jos? F. Mart?nez , Cornell University
Josep Torrellas , University of Illinois at Urbana-Champaign
pp. 126-134
Annual Index
93 ms
(Ver 3.1 (10032016))