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Issue No. 03 - May/June (2003 vol. 23)
ISSN: 0272-1732
pp: 46-57
Nick Richardson , STMicroelectronics
Lun Bin Huang , STMicroelectronics
Razak Hossain , STMicroelectronics
Julian Lewis , STMicroelectronics
Tommy Zounes , STMicroelectronics
Naresh Soni , STMicroelectronics
<p>A new implementation of the ST20-C2 CPU architecture involves an eight-stage pipeline with hardware support to execute up to three instructions per cycle. The design operates up to 520 MHz at 1.8V, among the highest reported speeds for a synthesized CPU core.</p>

R. Hossain, N. Soni, T. Zounes, L. B. Huang, J. Lewis and N. Richardson, "The iCore 520-MHz Synthesizable CPU Core," in IEEE Micro, vol. 23, no. , pp. 46-57, 2003.
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