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Issue No. 03 - May/June (2003 vol. 23)
ISSN: 0272-1732
pp: 46-57
Razak Hossain , STMicroelectronics
Naresh Soni , STMicroelectronics
Tommy Zounes , STMicroelectronics
Lun Bin Huang , STMicroelectronics
Julian Lewis , STMicroelectronics
Nick Richardson , STMicroelectronics
<p>A new implementation of the ST20-C2 CPU architecture involves an eight-stage pipeline with hardware support to execute up to three instructions per cycle. The design operates up to 520 MHz at 1.8V, among the highest reported speeds for a synthesized CPU core.</p>
Razak Hossain, Naresh Soni, Tommy Zounes, Lun Bin Huang, Julian Lewis, Nick Richardson, "The iCore 520-MHz Synthesizable CPU Core", IEEE Micro, vol. 23, no. , pp. 46-57, May/June 2003, doi:10.1109/MM.2003.1209466
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