Issue No.01 - January/February (2003 vol.23)
Published by the IEEE Computer Society
John W. Lockwood , Washington University in St. Louis
<p>Microcomputers and their users rely on interconnects to communicate. At the Hot Interconnects 10 conference, which took place 21 to 23 August 2002 at Stanford University, designers and architects from universities and companies met to discuss new technologies for high-performance switches, routers, and packet processing engines. These technologies enable computers and users to seamlessly exchange data over the Internet. They also transport data between multi-processors, interconnect clusters of workstations, and implement the core switching in storage area networks. </p>
Microcomputers and their users rely on interconnects to communicate. At the Hot Interconnects 10 conference, which took place 21 to 23 August 2002 at Stanford University, designers and architects from universities and companies met to discuss new technologies for high-performance switches, routers, and packet processing engines. These technologies enable computers and users to seamlessly exchange data over the Internet. They also transport data between multiprocessors, interconnect clusters of workstations, and implement the core switching in storage area networks.
The conference began with a keynote by Vint Cerf on delay-tolerant networking. Cerf, Arpanet pioneer and Transmission Control Protocol/Internet Protocol coauthor, described how space agencies are using Internet technology for interplanetary communications. The conference's second day began with a keynote by Eric Brewer, cofounder of Web search provider Inktomi. Brewer described why thinking beyond the traditional network layers is necessary when implementing new types of distributed services on the Internet.
In This Issue
The Hot Interconnects conference included 24 papers in six sessions. Attendees by vote chose the best articles, which appear in this issue of IEEE Micro. The first session addressed the challenges of building high-speed switches. An article from that session describes how designers built a single-stage packet switch that can process four terabits per second of data. François Abel et al. show how the switch elements are robust with respect to intraport communication delays and how the circuits map into ICs of practical size.
A challenge in building high-speed networks and multiprocessor systems is that interconnects can consume a significant amount of power. In fact, the power required to switch and route data between components constrains the size and speed of many systems. Hang-Sheng Wang, Li-Shiuan Peh, and Sharad Malik from Princeton University formulate an architectural-level model of power consumption. They have applied this model to commercial routers and shown it to provide accurate estimations of the average and maximum power consumed by each component.
To share bandwidth fairly, switches must carefully determine when to transmit each packet. Presenters described several ideas that reveal how new types of schedulers can multiplex packets fairly and process real-time data. Rong Pan et al. present a flow-table-based design that can approximate fairness for very high-speed switches.
To forward packets, Internet routers must classify packets using one or more packet header fields. Commercial routers typically use content-addressable memories to match multiple fields of the Internet header. Unfortunately, these CAMs can be expensive and inefficient. Samar Sharma and Rina Panigrahy of Cisco Systems presented several fast sorting and searching techniques using ternary CAMs.
To protect networks, firewalls must analyze the entire content of each data stream. This analysis can be tricky because each stream that flows through the Internet might be segmented into multiple packets, intermingled with other traffic flows, and appear at the firewall in a jumbled order. Recent research has focused on using network processors and/or customized hardware to perform these tasks. One article in this issue shows how to scan hundreds of thousands of TCP/IP data streams at multiple gigabit-per-second rates using a field-programmable gate array (FPGA) device.
In the final conference session, Hans Eberle presented a novel technique for monitoring and diagnosing computer systems. In his article, he describes how a system called Radioport embeds a small wireless transceiver into individual components that comprise a computing system. Using wireless links to communicate directly with the chips can reduce the time required to debug the whole system. Future designs could potentially use this technology to implement the Joint Test Action Group (JTAG) boundary scanning and configuration functions without wires.
Many Thank Yous
I thank several individuals who helped make Hot Interconnects 10 a success. Daniel Pitt led the steering committee, which included Mark Laubach, Allen Baum, Hasan Allchatib, Paul Borrill, and Glenn Langdon. Silvia Figueira and Peter Dommel served as the conference's general co-chairs. I served as the program chair. Sonia Fahmy organized the tutorials, and Liz Rogers served as the local chair and Webmaster. Dave Liddle moderated the panel on third-generation wireless networks. I also thank the 25 program committee members for diligently reviewing and commenting on each conference paper and those that ultimately appear in this issue.
Hot Interconnects 11 will take place in August 2003, once again at Stanford University, starting the day after Hot Chips. If you are interested in participating in the conference, please visit http://www.hoti.org.
John W. Lockwood is a professor of computer science at Washington University in St. Louis. His research interests include design and implementation of networking systems in reconfigurable hardware. Lockwood has BS, MS, and PhD degrees in electrical and computer engineering from the University of Illinois. He will serve as the general chair for the upcoming Hot Interconnects 11 and has served as the program chair for Hot Interconnects 10. He will also serve as the program chair for the upcoming International Conference on Microelectronic Systems Education, and has served on the technical program committee for the International Working Conference on Active Networks. He has reviewed articles for the IEEE Journal on Selected Areas of Communication, IEEE Transactions on Very Large Scale Integration Systems, ACM Transactions on Embedded Systems, ACM SIGMETRICS, the Computer Networks Journal, and Globecom. He is a member of IEEE, ACM, Tau Beta Pi, and Eta Kappa Nu.