Issue No. 05 - September/October (2002 vol. 22)
<p>Parallel testing of cores can reduce soc test times, but the finite number of chip I/Os limits such parallelism. Space and time compaction can maximize parallelism by minimizing the required test bandwidth at the core outputs.</p>
O. Sinanoglu and A. Orailoglu, "Efficient Construction of Aliasing-Free Compaction Circuitry," in IEEE Micro, vol. 22, no. , pp. 82-92, 2002.