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ABSTRACT
<p>Parallel testing of cores can reduce soc test times, but the finite number of chip I/Os limits such parallelism. Space and time compaction can maximize parallelism by minimizing the required test bandwidth at the core outputs.</p>
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CITATION

O. Sinanoglu and A. Orailoglu, "Efficient Construction of Aliasing-Free Compaction Circuitry," in IEEE Micro, vol. 22, no. , pp. 82-92, 2002.
doi:10.1109/MM.2002.1044302
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