Issue No. 05 - September/October (2002 vol. 22)
<p>The Eclipse network-on-a-chip architecture uses a sophisticated parallel programming model, realized through multithreaded processors, interleaved memory modules, and a high-capacity interconnection network to support system-on-a-chip designs.</p>
M. Forsell, "A Scalable High-Performance Computing Solution for Networks on Chips," in IEEE Micro, vol. 22, no. , pp. 46-55, 2002.