Issue No. 05 - September/October (2002 vol. 22)
<p>Latency-insensitive design is the foundation of a correct-by-construction methodology for SOC design. This approach can handle latency's increasing impact on deep-submicron technologies and facilitate the reuse of intellectual-property cores for building complex systems on chips, reducing the number of costly iterations in the design process.</p>
L. P. Carloni and A. L. Sangiovanni-Vincentelli, "Coping with Latency in SOC Design," in IEEE Micro, vol. 22, no. , pp. 24-35, 2002.