The Community for Technology Leaders
Green Image
ABSTRACT
<p>Latency-insensitive design is the foundation of a correct-by-construction methodology for SOC design. This approach can handle latency's increasing impact on deep-submicron technologies and facilitate the reuse of intellectual-property cores for building complex systems on chips, reducing the number of costly iterations in the design process.</p>
INDEX TERMS
CITATION
Luca P. Carloni, Alberto L. Sangiovanni-Vincentelli, "Coping with Latency in SOC Design", IEEE Micro, vol. 22, no. , pp. 24-35, September/October 2002, doi:10.1109/MM.2002.1044297
97 ms
(Ver 3.1 (10032016))