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ABSTRACT
<p>Latency-insensitive design is the foundation of a correct-by-construction methodology for SOC design. This approach can handle latency's increasing impact on deep-submicron technologies and facilitate the reuse of intellectual-property cores for building complex systems on chips, reducing the number of costly iterations in the design process.</p>
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CITATION

L. P. Carloni and A. L. Sangiovanni-Vincentelli, "Coping with Latency in SOC Design," in IEEE Micro, vol. 22, no. , pp. 24-35, 2002.
doi:10.1109/MM.2002.1044297
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