Issue No. 03 - May/June (2002 vol. 22)
<p>The authors propose a learning-hardware approach as a generalization of evolvable hardware. A massively parallel, reconfigurable processor speeds up logic operators performed in learning hardware. The approach uses combinatorial synthesis methods developed within the framework of the logic synthesis in digital-circuit-design automation. </p>
M. Perkowski, D. Foote, Q. Chen, A. Al-Rabadi and L. Jozwiak, "Learning Hardware Using Multiple-Valued Logic, Part 1: Introduction and Approach," in IEEE Micro, vol. 22, no. , pp. 41-51, 2002.