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Guest Editors' Introduction: Hot Chips 13

John , University of California, Berkeley
Andrew , SONICblue

Pages: pp. 6-7

Many of today's startling advances in computing technology are direct consequences of Moore's law related growth in transistor count, computational performance, and network bandwidth. Although technologists provide an increasing number of components on chip with each passing generation, it is the chip designers and computer architects who use this technology and drive the Moore's law curve. Microprocessor performance has doubled every 18 months for several decades, leading to a vast array of interesting applications.

Over its 13-year history, the Hot Chips conference has become a leading forum for the latest computing, communications, and networking chips. The conference covers technical details of these chips across the board, including technology, fundamental algorithms, packaging techniques, architecture, and circuit details. The emphasis is on real chips and applications; not theoretical research or marketing hype.

The 2001 Hot Chips 13 program consisted of 25 wonderful presentations selected from a set of high-quality submissions. This year saw a continued trend away from traditional high-performance computing toward embedded applications, networking, infrastructure chips, and even micromagnetic storage devices. This issue of IEEE Micro brings you the best of these presentations expanded to full articles.


The ability to store gigabytes of information in handheld packages has fundamentally changed the way that we view the accessibility of information. As a result, this year's program committee accepted several talks about storage devices. David Davies' article describes the DataPlay storage media and player. DataPlay has set new standards for compact storage by storing up to 500 Mbytes of information on a 32-mm optical disc. Davies discusses some of the interesting challenges involved with the DataPlay recording technology, as well as its digital rights management features.


Over the years, computer architects have scrambled to increase the performance of computing systems, often at the expense of reliability, availability, and durability. A new awareness of the importance of reliability (and related metrics) has arisen in academia and industry alike. For example, companies such as IBM have launched new initiatives like the autonomic computing initiative ( to study self-repairing systems.

In search of more reliable systems, computer architects have added features to assist in diagnosing and repairing computer systems. In their article, Douglas Bossen, Joel Tendler, and Kevin Reick discuss the features that IBM has added to the Power4 architecture to aid reliability. Features such as these will become common in all processing chips.


As the number of transistors on a processor chip rapidly approaches the one billion mark, computer architects search for new and different ways to structure their chips. Faced with diminishing returns from out-of-order execution and on-chip caching, architects have turned toward chip multiprocessors as a possible solution.

Michael Taylor and his colleagues at MIT describe the experimental Raw chip, which includes 16 processors and a programmable interconnection network. Through an innovative combination of architecture and compiler technology, the Raw chip heralds a whole new class of chip microprocessors.


Although multiprocessing has long been available for specialized applications, Intel continues to push multiprocessing toward the mainstream.

In their article, FayƩ Briggs et al. describe the 870 chipset. This chipset forms a substrate on which to tie together 16 or more Pentium-4-class processors into a shared-memory multiprocessor. The result is inexpensive and scalable multiprocessing. With the rising popularity of explicitly threaded languages, such as Java, and processor-intensive, parallelizable multimedia applications, we will doubtlessly see a rise in the consumer applications of multiprocessing.


InfiniBand is a new industry standard that promises to increase available input/output bandwidth by one or more orders of magnitude. It is a switched, point-to-point channel architecture that supports three link speeds: 2.5, 10, and 30 gigabits per second. In his article, Chris Eddington describes InfiniBridge, which combines PCI communication and InfiniBand switching in a single chip. It even supports transparent PCI-to-PCI bridging over the InfiniBand fabric.


Space limitations prevent us from including more presentations from Hot Chips 13. Most of these presentations, as well as others from previous years are available at We hope that you find these articles as exciting as we do.

About the Authors

John Kubiatowicz is an assistant professor of electrical engineering and computer science at the University of California, Berkeley. His specialties include computer architecture, operating systems, and networking. His research interests include speculative approaches for computer design, such as quantum, biological, and autonomic computing, as well as issues in Internet-scale systems design, namely security, privacy, and denial-of-service resilience. He currently leads the OceanStore research effort (, which is exploring a utility storage architecture that targets millions of servers and billions of users. He is also exploring architectures for quantum transport in quantum computers. Kubiatowicz has a PhD in electrical engineering and computer science from the Massachusetts Institute of Technology, where he was one of the principle designers of the Alewife multiprocessor. He also holds dual BS degrees in electrical engineering and physics, and an MS in electrical engineering and computer science from MIT.
Andrew Wolfe is the senior vice president and chief technical officer of SONICblue. As CTO, he directs product strategy, technology policy, and industry partnerships. He has successfully acquired and integrated five emerging technology companies in the advanced digital-entertainment space to create the current SONICblue. Before joining SONICblue, Wolfe was an assistant professor of electrical engineering at Princeton University. He is currently a consulting professor at Stanford University. He holds four patents, has been published in over twelve journals, and has presented over 40 conference papers. He holds a BSEE from the Johns Hopkins University and an MS and a PhD in computer engineering from Carnegie Mellon University.
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