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In the September/October 2001 issue, the print version of "Online Check and Recovery Techniques for Dependable Embedded Processors," pp. 24-40, by Matthias Pflanz and Heinrich Theodor Vierhaus, contains errors. On p. 26, right column, the second line should read "Berger code prediction is another hardware redundancy technique with an overhead below that of duplication; BCP detects errors by comparing precalculated and real code." In Table 2, the data path's correct number of registers is eight. In Figure 6, the box labeled "Central signal prediction unit" should read "Control signal prediction unit." In Figures 8a and 8b, the label "Tracker" should read "Trailer." In the bottom right of Figure 8a, "Cycle 1" should read "Cycle 3." In Figure 11, there is an alteration in a line (next to the D) that goes to the register file.

Also, the last three words of Micro Economics pp. 6-7, 10, by Shane Greenstein, were missing. These words were "...failures will follow."

Please see our Digital Library at for the correct version of this article and this department. IEEE Micro regrets these errors.

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