, Pacific Broadband Communications
, Nortel Networks
Pages: pp. 14-15
The Hot Interconnects VIII Symposium (HotI 8) took place during 16-18 August 2000, at Stanford University. If you were among the almost 400 attendees during those few days, you would have no doubt noticed several individuals roaming about dressed in loud, bright yellow Hawaiian shirts decorated with red hot chili peppers. The staff of HotI 8 picked the uniform not only to stand out in the crowd but also as a reflection of the red hot papers and ideas presented during the symposium.
As in previous years, HotI 8 focused on high-performance interconnects, from system buses and interfaces to networks. The unique forum brought together designers and architects of high-performance chips, software, and systems in one auditorium. Presentations focused on up-to-the-minute real developments from academia and leading-edge companies, large and small. In addition, two days of tutorials following the technical sessions covered topics that span ultra-wideband wireless, voice over IP (VoIP), optical networking, and packet classification.
Dave Farber, the chief technologist of the Federal Communications Commission gave the opening keynote. Dave demystified the inner workings of the US Federal Communications Committee and enlightened the crowd with his views on the future of the industry. Presenting an outsider's inside view of technology, Dan Gillmor, technology columnist from the San Jose Mercury News talked about alarming issues facing technical innovation and intellectual property.
The hot-button panel discussion topic this year was "What's the Future of Broadband Wireless?" The evening panel presented leading industry experts under the direction of moderator Robert J. Berger (UltraDevices). Panelists Dewayne Hendricks (The Dandin Group), Arogyaswami Paulraj (Gigabitwireless), Ralph Petroff (Time Domain), Ender Ayanoglu (Cisco Systems), and Hatim Zaghloul (WiLAN) addressed the technical directions of the industry and the politics of frequency allocation.
HotI's main focus is, of course, the technical papers. From these presentations, the HotI Program Committee selected six to be published in this special issue of IEEE Micro. They were judged to be of high quality and to echo the common theme of addressing bottlenecks that exist at different levels of system interconnects. These articles range from clustered systems to router design and performance analysis to component I/O technology.
We've ordered the articles in a top-down approach, starting with one on cluster computing, three on router design, one on switch design, and finally one on high-speed interconnect design. The first, "CLARA: A Cluster-Based Active Router Architecture" by Welling, Ott, and Mathur, describes a distributed architecture that provides a scalable computational service within a network. In addition the authors present real-life experiences of realizing the architecture using off-the-shelf PCs.
"A Delay Model for Router Microarchitectures" by Peh and Dally proposes a router model that takes into account the pipelined nature of router architecture and applies the model to derive realistic pipelines for comparing wormhole and virtual circuit routers. Compared to several models currently in use, the model more accurately predicts latency behavior for use in optimizing network performance. "Fast Updating Algorithm for TCAMs" by Shah and Gupta describes techniques to improve routing lookups and packet processing. It proposes two algorithms to manage the ternary content-addressable memory (TCAM) that is in the critical path of all incoming packets in a router. The simulation results show significant performance benefits achievable using these algorithms.
"Approximate Fair Dropping for Variable-Length Packets" by Psounis, Pan, and Prabhakar describes a technique to improve network performance by better queue management in routers. This technique provides fair bandwidth allocation while maintaining a low implementation cost and improving upon a similar scheme introduced earlier by the authors. This article also goes into some of the implementation issues and should be a good reference for those involved in the development of routers. Rounding off the section on routers is "A Terabit Multiservice Switch." Author Yun describes the Cyclone switch architecture that provides scalable multiterabits of switching capacity in five custom ASICs. The architecture provides wire-speed scheduling necessary to support the quality of service for eight classes of service, including TDM.
The final article, "JAZiO Signal Switching Technology: A Low-Cost Digital I/O for High-Speed Applications" by Haq et al. describes a digital signal switching technique that uses differential sensing but requires only a single pin per signal. It's based on detecting a change or no-change from the previous state instead of the traditional high or low voltage compared to a reference. JAZiO is suitable for low-latency, burst-mode operations for high-speed interchip or intrachip signal transfers. The technology can be applied to various components.
We hope you find this collection of articles as informative and useful as we did. As a final note, we acknowledge the contributions of the HotI Program Committee and other reviewers, Mark Laubach, the HotI 8 conference chair, and the entire staff of HotI 8.
Please visit www.hoti.org for information about the Hot Interconnects Symposium. HotI9 meets again in August 2001.