Issue No. 06 - November/December (2000 vol. 20)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/40.888704
The IA-64 architecture has a rich set of features including control and data speculation, predication, large register files, and an advanced branch architecture, which allow the compiler to exploit instruction-level parallelism (ILP) and optimize applications in many new ways. The Intel IA-64 compiler incorporates i) state-of-the-art optimization techniques known in the compiler community, ii) optimization techniques that are extended to exploit the resources and features in IA-64, and iii) new optimization techniques designed for IA-64.
David Sehr, Daniel Lavery, Dattatraya Kulkarni, Wei Li, Rakesh Krishnaiyer, Chu-cheow Lim, John Ng, "An Advanced Optimizer for the IA-64 Architecture", IEEE Micro, vol. 20, no. , pp. 60-68, November/December 2000, doi:10.1109/40.888704